
30092624
FIGURE 17. VDD Charge Pump Circuit
The circuit in
Figure 17 will effectively supply close to the VDD
voltage (4.5V) between the gate and the source of the high-
side MOSFET during the on time. It is recommended to use
a Schottky diode for D
BOOT with sufficient reverse standoff
voltage and continuous current rating. The average current
through this diode is dependent on the gate charge of the
high-side FET and the frequency. It can be calculated using
the following equation
I
DBOOT is the average current through the DBOOT diode, fSW
(Hz) is the switching frequency and Q
GHS (C) is the gate
charge of the high-side MOSFET. If the input voltage is below
5.5V, it is recommended to connect VDD to the input supply
of the LM27402 through a 1
This will increase the gate voltage of both the low-side and
high-side FETs.
30092632
FIGURE 18. Tie V
DD to VIN when VIN ≤ 5.5V
POWER / EFFICIENCY CALCULATIONS
The overall efficiency of a buck regulator is simply the ratio of
output power to input power. Accurately predicting the overall
efficiency can be tedious and depends on many variables.
Although power losses can be found in almost every compo-
nent of a buck regulator, the following sections present equa-
tions detailing components with the highest relative power
loss.
MOSFETS
Selecting the correct MOSFET for a design is important to the
overall operation of the circuit. If inappropriate FETs are se-
lected for the application, it can result in poor efficiency, high
temperature issues, shoot-through and other impairments. It
is important to calculate the power dissipation for each MOS-
FET at the maximum output current and make sure the max-
imum allowable power dissipation is not exceeded. MOSFET
datasheets should also specify a junction-to-ambient thermal
resistance (
θ
JA) so the temperature rise can be estimated
from this specification .
Both high-side and low-side FETs contribute significant loss
to the system relative to the other components. The high-side
FET contributes transition switching losses, conduction loss-
es and gate charge losses. The low-side FET also contributes
conduction and gate charge losses, but the FET body diode
voltage drop during deadtime and reverse recovery loss must
also be considered. The transition losses for the low-side FET
are small and usually ignored.
High-Side MOSFET
The next set of equations can be used to calculate the losses
associated with the high-side FET.
P
CND_HS is the conduction loss of the high-side FET during the
D cycle when current is flowing through the FET on-resis-
tance. A self heating coefficient of 1.3 is included in this
equation to approximate the effects of the R
DS(ON) tempera-
ture coefficient. R
DS(ON)_HS () is the drain to source resis-
tance, I
OUT (A) is the output current and D is the duty ratio.
P
SW_HS is the switching power loss during the high-side FET
transition time. V
IN (V) is the input voltage, fSW (Hz) is the
switching frequency, and t
r and tf (s) are the rise and fall times
of the switch-node voltage respectively. P
TOT_HS is the total
power dissipation of the high-side FET.
The gate charge of the high-side MOSFET can greatly affect
the turn-on transition time and therefore efficiency. Further-
more, it is wise to consider the ratio of switching loss to
conduction loss associated with the high-side FET. If the duty
ratio is small and the input voltage is high, it may be beneficial
to tradeoff Q
G for higher RDS(ON) to avoid high switching losses
relative to conduction losses. If the duty ratio is large and the
input voltage is low, then a lower R
DS(ON) FET in tandem with
a higher Q
G may result in less power dissipation.
Low-Side MOSFET
The next set of equations can be used to calculate the losses
due to the low-side FET.
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LM27402