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參數(shù)資料
| 型號： | LM2702MT-ADJ/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.6 A SWITCHING REGULATOR, 720 kHz SWITCHING FREQ-MAX, PDSO16 |
| 封裝： | TSSOP-16 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 1197K |
| 代理商： | LM2702MT-ADJ/NOPB |
Operation (Continued)
Where R
L is the minimum load resistance corresponding to
the maximum load current. The zero created by the ESR of
the output capacitor is generally very high frequency if the
ESR is small. If low ESR capacitors are used it can be
neglected. If higher ESR capacitors are used see the High
Output Capacitor ESR Compensation section.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right
half plane zero (RHP zero). This zero has the effect of a zero
in the gain plot, causing an imposed +20dB/decade on the
rolloff, but has the effect of a pole in the phase, subtracting
another 90 in the phase plot. This can cause undesirable
effects if the control loop is influenced by this zero. To ensure
the RHP zero does not cause instability issues, the control
loop should be designed to have a bandwidth of less than 12
the frequency of the RHP zero. This zero occurs at a fre-
quency of:
where I
LOAD is the maximum load current.
SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components R
C
and C
C is to set a dominant low frequency pole in the control
loop. Simply choose values for R
C and CC within the ranges
given in the Introduction to Compensation section to set this
pole in the area of 10Hz to 500Hz. The frequency of the pole
created is determined by the equation:
where R
O is the output impedance of the error amplifier,
approximately 1M
. Since R
C is generally much less than
R
O, it does not have much effect on the above equation and
can be neglected until a value is chosen to set the zero f
ZC.
f
ZC is created to cancel out the pole created by the output
capacitor, f
P1. The output capacitor pole will shift with differ-
ent load currents as shown by the equation, so setting the
zero is not exact. Determine the range of f
P1 over the ex-
pected loads and then set the zero f
ZC to a point approxi-
mately in the middle. The frequency of this zero is deter-
mined by:
Now R
C can be chosen with the selected value for CC.
Check to make sure that the pole f
PC is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure
both component values are in the recommended range. After
checking the design at the end of this section, these values
can be changed a little more to optimize performance if
desired. This is best done in the lab on a bench, checking the
load step response with different values until the ringing and
overshoot on the output voltage at the edge of the load steps
is minimal. This should produce a stable, high performance
circuit. For improved transient response, higher values of R
C
should be chosen. This will improve the overall bandwidth
which makes the regulator respond more quickly to tran-
sients. If more detail is required, or the most optimal perfor-
mance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or
just to improve the overall phase margin of the control loop,
another pole may be introduced to cancel the zero created
by the ESR. This is accomplished by adding another capaci-
tor, C
C2, directly from the compensation pin VC to ground, in
parallel with the series combination of R
C and CC. The pole
should be placed at the same frequency as f
Z1, the ESR
zero. The equation for this pole follows:
To ensure this equation is valid, and that C
C2 can be used
without negatively impacting the effects of R
C and CC,fPC2
must be greater than 10f
ZC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a
bandwidth of 12 or less of the frequency of the RHP zero.
This is done by calculating the open-loop DC gain, A
DC. After
this value is known, you can calculate the crossover visually
by placing a 20dB/decade slope at each pole, and a +20dB/
decade slope for each zero. The point at which the gain plot
crosses unity gain, or 0dB, is the crossover frequency. If the
crossover frequency is less than 12 the RHP zero, the phase
margin should be high enough for stability. The phase mar-
gin can also be improved by adding C
C2 as discussed earlier
in the section. The equation for A
DC is given below with
additional equations required for the calculation:
mc ) 0.181fs (in V/s)
where R
L is the minimum load resistance, VIN is the mini-
mum input voltage, g
m is the error amplifier transconduc-
tance found in the Electrical Characteristics table, and R
D-
SON
is the value chosen from the graph "R
DSON vs. VIN "in
the Typical Performance Characteristics section.
LM2702
www.national.com
18
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