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參數(shù)資料
| 型號： | LM2645MTD/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 335 kHz SWITCHING FREQ-MAX, PDSO48 |
| 封裝： | TSSOP-48 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 911K |
| 代理商： | LM2645MTD/NOPB |
Operation Descriptions (Continued)
NEGATIVE CURRENT LIMIT
The purpose of negative current limit is to ensure that the
inductor will not saturate during negative current flow caus-
ing excessive current to flow through the bottom FET. The
negative current limit is realized through sensing the bottom
FET Vds. An internally generated 100mV (typical) is used to
compare with the bottom FET Vds when it is on. Upon
sensing too high a Vds, the bottom FET will be turned off.
The negative current limit is activated in force PWM mode.
OVER-VOLTAGE PROTECTION
This protection feature is implemented in the two switching
channels and not the linear channels. Any over voltage event
at any of the two switching channels’ output will cause the
LM2645 to enter the shut down latch state. The HDRVx will
be turned off, and the LDRVx will be turned on immediately
to drive the bottom FET to discharge the output capacitor
through the filter inductor.
UNDER-VOLTAGE PROTECTION
The UVP feature is implemented in channel 1, channel 2 and
the linear regulator controller (LDODRV). The under-voltage
protection feature is disabled if the UV_DELAY pin is pulled
to ground; this is useful for system debug work. If a capacitor
is connected between the UV_DELAY pin and ground, and
the voltage at the SSx pin is above 2V, the UVP is at ready
mode.
If a switching channel is enabled, and its soft-start time out
signal, sstox (see soft start section) is asserted, then an
under-voltage event at the output of that channel will cause
the system to enter the UVP timeout state. For the external
linear regulator controller (LDODRV), if channel 1 is on and
the soft start time out signal (ssto1) has been issued, then an
under voltage event at the linear regulator output will cause
the system to enter UVP timeout state.
When the system reacts on an under-voltage event, a 5A
current will charge the capacitor connected to the UV_DE-
LAY pin; when the capacitor is charged to a voltage exceed-
ing 2.3V(typical), the system immediately enters shut down
latch state.
POWER GOOD FUNCTION
Two power good signals are available for indicating the
general health of the two switching channels individually.
The function is realized through the internal MOSFET of
each channel tied from the PGOODx pins to ground. The
power good signal is asserted by turning off the MOSFET of
that channel. The on resistance of the power good MOSFET
is about 300
.
The internal power good MOSFET will not be turned on
unless at least one of the following occurs:
1.
there is an output over voltage event;
2.
the output voltage is below the power good lower limit;
3.
system is in the shut down mode, i.e. the SD pin voltage
is below 0.6V;
4.
The switching channel is in standby mode, i.e. the ONx
pin is below 0.8V;
5.
system is in the fault state.
6.
system is in the shut down latch state.
Power good upper limit is the same as that of the OVP
threshold.
Except in the latched off condition (cases 1 and 6) , if the
corresponding output voltage(s) recovers to within 6% of
regulation, PGOODx will be asserted again. But there is a
built-in hysteresis. See V
pwrgd in the Electrical Characteris-
tics table. The above information is also available in Power
Good Truth Table.
VLIN5, VDDx and EXT
An internal 5V supply (VLIN5) is generated from the VIN
voltage through an internal linear regulator. This 5V supply is
mainly for internal circuitry use, but can also be used exter-
nally. When used externally, it is recommended that the
VLIN5 voltage only be used for powering the gate drivers,
i.e. supplying the bias for the top drivers’ bootstrap circuit
and the bottom drivers’ VDDx pins.
When the voltage applied to the EXT pin is below 4.7V, an
internal 5V low dropout regulator supplies the power for the
VLIN5. If the EXT voltage is taken above 4.7V, the 5V
regulator is turned off and an internal switch is turned on to
connect the EXT pin to the VLIN5 pin. This allows the VLIN5
power to be derived from a high efficiency source such as
the output from either one of the switching channels, when
the channel is configured to operate in fixed 5V mode.
Irrespective of the signals on the ONx pins, the VLIN5 volt-
age output will come from the EXT pin whenever the voltage
applied to the EXT pin is higher than 4.7V. The externally
applied voltage is required to be less than the voltage ap-
plied to the VIN pin at all times, even when both channels are
shut down. This prevents a voltage back feed situation from
the EXT pin to the VIN pin.
In shut down mode the VLIN5 pin may go as high as 6.5V.
Connecting a 100k
dummy load from VLIN5 to ground will
hold the voltage to 6V maximum. Using a 200k
resistor to
pull up PGOOD1 and PGOOD2 to VLIN5 is an alternative
solution.
When input voltage is guaranteed to be within 4.5V to 5.5V,
tie the VLIN5 pin directly to the VIN pin and tie the EXT to
ground. In this mode, the VLIN5 current directly comes from
power stage input rail and power loss due to the internal
linear regulation is no longer an issue.
The two VDDx pins can be tied together. Always connect
them to the VLIN5 pin through a 4.7
resistor and connect a
ceramic capacitor of at least 1F to bypass the VDDx pins to
ground.
OUTPUT CAPACITORS FOR LINEAR REGULATORS
Like any linear regulator, each linear output that is either
generated or controlled by the LM2645 requires an output
capacitor to ensure stability. The output of OUT3 needs a
capacitor of 1F minimum. The VLIN5 needs a minimum of
4.7F. Channel 4, the linear regulated output rail that is
controlled by the LDODRV pin, requires an output capacitor
of 10F minimum to prevent oscillation.
In applications where the OUT3 is not needed, it may be
disabled by connecting this pin to the VLIN5 as illustrated in
Figure 3 to eliminate the need of a output capacitor.
LM2645
www.national.com
17
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