參數(shù)資料
型號(hào)： LM2645MTD/NOPB
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 穩(wěn)壓器
英文描述： SWITCHING CONTROLLER, 335 kHz SWITCHING FREQ-MAX, PDSO48
封裝： TSSOP-48
文件頁(yè)數(shù)： 8/20頁(yè)
文件大?。?/td> 911K
代理商： LM2645MTD/NOPB
Operation Descriptions (Continued)
The force-PWM mode is good for applications where fixed
switching frequency is required.
In force-PWM mode, the top FET has to be turned on for a
minimum of typically 220ns each cycle. However, when the
required duty cycle is less than the minimum value, the skip
comparator will be activated and pulses will be skipped to
maintain regulation.
SKIP COMPARATOR
Whenever the output voltage of the error amplifier (COMPx
pin) goes below a 0.5V threshold, the PWM cycles will be
"skipped" until that voltage exceeds the threshold again.
PULSE-SKIP MODE
This mode is activated by pulling the FPWM/2NDFB pin to a
TTL-compatible logic high and applies to both switching
channels simultaneously. In this mode, the 0-CROSSING /
NEGATIVE CURRENT LIMIT comparator detects the bottom
FET current. Once the bottom FET current flows from drain
to source, the bottom FET will be turned off. This prevents
negative inductor current. In force-PWM operation, the in-
ductor current is allowed to go negative, so the regulator is
always in Continuous Conduction Mode (CCM), no matter
what the load is. In CCM, duty cycle is almost independent of
the load and is roughly Vout divided by Vin. In pulse-skip
mode, the regulator enters Discontinuous Conduction Mode
(DCM) under light load. Once the regulator enters DCM, its
switching frequency droops as the load current decreases.
The regulator operates in DCM PWM mode until its on-time
falls below 85% of the CCM on-time, then the MIN_ON-
_TIME comparator takes over. It forces 85% of the CCM
on-time thus causing the output voltage to continuously rise
and COMPx pin voltage (error amplifier output voltage) to
continuously droop. When the COMPx pin voltage hits the
0.5V level, the CYCLE_SKIP comparator toggles, causing
the present switching cycle to be "skipped", i.e., both FETs
remain off during the whole cycle. As long as the COMPx pin
voltage is below 0.5V, no switching of the FETs will happen.
As a result, the output voltage will droop, and the COMPx pin
voltage will rise. When the COMPx pin goes above the 0.5V
level, the CYCLE_SKIP comparator flips and allows a 85%
CCM on-time pulse to happen. If the load current is so small
that this single pulse is enough to bring the output voltage up
to such a level that the COMPx pin drops below 0.5V again,
the pulse skipping will happen again. Otherwise it may take
a number of consecutive pulses to bring the COMPx pin
voltage down to 0.5V again. As the load current increases, it
takes more and more consecutive pulses to drive the
COMPx voltage to 0.5V. When the load current is so high
that the duty cycle exceeds the 85% CCM on-time, then
pulse-skipping disappears. In pulse-skip mode, the fre-
quency of the switching pulses decrease as the load current
decreases. Since the load is usually very light in pulse-skip
mode, conducted noise will be very low and the variable
operating frequency should cause no EMI problems in the
system.
The LM2645 pulse-skip mode helps the light load efficiency
for two reasons. First, it turns on the bottom FET only when
inductor current is in positive conduction region, this elimi-
nates circulating energy loss. Second, the FETs are switch-
ing only when necessary, rather than every cycle, that re-
duces FETs switching loss and gate drive power loss.
CURRENT SENSING AND CURRENT LIMITING
The information of inductor current is extracted by the cur-
rent sense pin KSx and RSNSx. As shown in Figure 1 and
Figure 2, current sensing is accomplished by either sensing
the Vds of the top FET, or sensing the voltage across a
current sense resistor connected from Vin to the drain of the
top FET. The advantage of sensing current across the top
FET is reduced parts count and cost. Using a current sense
resistor improves current sense accuracy. To ensure linear
operation of the current amplifier, the current sense voltage
input must not exceed 200mV. Therefore, the Rds of the top
FET or the current sense resistor must be small enough that,
when the top FET is on, the current sense voltage does not
exceed 200mV.
There is a leading edge blanking circuit that forces the top
FET to be on for at least 150ns. Beyond this minimum on
time, the output of the PWM comparator is used to turn off
the top FET.
With an external resistor connected between the ILIMx pin
and the KSx pin, the 10A current sink on the ILIMx pin
produces a voltage across the resistor to serve as the refer-
ence voltage for current limit. Adding a 10nF capacitor
across this resistor will filter unwanted noise that could im-
properly trip the current limit comparator. Current limit is
activated if the inductor current is too high causing the
voltage at the RSNSx pin to be lower than that of the ILIMx
pin, toggling the comparator thus turning off the top FET
immediately. The comparator is disabled either when the top
FET is turned off or during the leading edge blanking time.
20015928
FIGURE 1. Current Sensing by Vds of the Top FET
20015929
FIGURE 2. Current Sensing by External Sense Resistor
LM2645
www.national.com
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