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參數(shù)資料
| 型號： | LM2637MWC |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, UUC |
| 封裝： | WAFER |
| 文件頁數(shù)： | 19/20頁 |
| 文件大?。?/td> | 404K |
| 代理商： | LM2637MWC |
Pin Description
Pin
Pin Name
Pin Function
1
LG
Low side N-FET gate driver output.
2
PGND
Ground for the two FET drivers of the switching section.
3V
DD
Supply for the FET gate drivers. Usually tied to +12V.
4
SNS2
Feedback pin for the 1.5V linear regulator.
5
G2
Gate drive output for the external N-MOS of the fast 1.5V linear regulator.
6
SGND
Ground for internal signal circuitry and system ground reference.
7V
CC
Supply voltage. Usually +5V.
8
SNS1
Output voltage monitor input for the switching regulator.
9
CS+
Switching regulator current sense input, positive node.
10
CS
Switching regulator current sense input, negative node.
11
OVP
Over-voltage protection output for the switching regulator. Can be used to fire an external
SCR.
12
FREQ
Switching frequency adjustment pin. An external resistor is needed to set the desired
frequency.
13
EAO
Output of the error amplifier. Used for compensating the switching regulator.
14
FB
Inverting input of the error amplifier. Used for compensating the switching regulator.
15
PWGD
Open collector Power Good signal.
16
VID4
5-Bit DAC input, MSB.
17
VID3
5-Bit DAC input.
18
VID2
5-Bit DAC input.
19
VID1
5-Bit DAC input.
20
VID0
5-Bit DAC input, LSB.
21
G3
Gate drive pin for the external N-MOS of the 2.5V linear regulator.
22
SNS3
Feedback pin for the 2.5V linear regulator.
23
EN
Output Enable. A logic low shuts the whole chip down.
24
HG
High side N-FET gate driver output.
Applications Information
OVERVIEW
The LM2637 provides control and protection for three volt-
age regulators. Namely, a synchronous buck switching con-
troller and two linear regulator controllers that drive an exter-
nal N-FET or NPN transistor.
Switching Section — The switching controller features a
VRM-compatible,
5-bit
programmable
output
voltage,
over-current and over-voltage protection, under-voltage
latch-off, a power good signal, and an output enable. The
5-bit DAC has a typical tolerance of 1%. There are two
user-selectable over-current protection methods. One pro-
vides accurate over-current protection with the use of an ex-
ternal sense resistor. The other saves cost by taking advan-
tage of the r
DS_ON of the high-side FET. The over-voltage
protection provides two levels of protection. The first turns off
the high-side FET and turns on the low-side. The second
provides a gate signal that can be used to fire an external
SCR.
The PWM frequency is adjustable from 50 kHz to beyond 1
MHz through an external resistor.
Soft start is realized through an internal digital counter. No
external soft start capacitor is necessary.
Dynamic positioning of the switcher output voltage reduces
the number of output capacitors and can be easily realized
using the same sense resistor as the over-current protection.
Linear Section — The two linear regulator controllers feature
wide control bandwidth, N-FET and NPN transistor driving
capability, an adjustable output voltage and a typical 2% tol-
erance. The wide control bandwidth makes meeting the
GTL+ bus transient response requirement an easy job.
When no external resistor divider is used, the two controllers
default to 1.5V and 2.5V respectively.
Both linear sections have under-voltage latch-off. Should the
output voltage drop below 0.63V, the corresponding gate
drive will be disabled and PWGD pin will be pulled low.
THEORY OF OPERATION
Start Up
Switching Section — The soft start circuitry starts to work
when three conditions are met, i.e., EN pin is a logic high, the
VID code is valid and V
CC pin voltage exceeds 4.2V. The du-
ration of the soft start is determined by an internal digital
counter and the switching frequency. During soft start, the
output of the error amplifier is allowed to increase gradually.
When the counter has counted 4,096 clock cycles, soft start
session ends and the output level of the error amplifier is re-
leased and allowed to go to a value that is determined by the
feedback loop. PWRGD pin is always low during soft start
and is turned over to output voltage monitoring circuitry after
that. Before V
CC
reaches 4V, all internal logic is in a
power-on-reset state and the two FET drivers are disabled.
www.national.com
8
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