參數(shù)資料
型號(hào): LM1971
廠商: National Semiconductor Corporation
英文描述: LM1971 Overture⑩ Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with/Mute
中文描述: LM1971音頻序曲⑩衰減器系列數(shù)控六十二分貝音頻衰減器與/靜音
文件頁(yè)數(shù): 6/11頁(yè)
文件大?。?/td> 248K
代理商: LM1971
Application Information
SERIAL DATA FORMAT
The LM1971 uses a 3-wire serial communication format that
is easily controlled by a microcontroller. The timing for the
3-wire set, comprised of DATA, CLOCK, and LOAD is shown
in Figure 2 As depicted in Figure 2 the LOAD line is to go
low at least 150 ns before the rising edge of the first clock
pulse and is to remain low throughout the transmission of the
16 data bits. The serial data is composed of an 8-bit address,
which must always be set to 0000 0000 to select the single
audio channel, and 8 bits for attenuation setting. For both ad-
dress data and attenuation setting data, the MSB is sent first
with the address data preceding the attenuation data. Please
refer to Figure 3 to confirm the serial data format transfer
process.
Table 1 shows the various Address and Data byte values for
different attenuation settings. Note that Address bytes other
than 0000 0000 are ignored.
μPOT SYSTEM ARCHITECTURE
The μPot’s digital interface is essentially a shift register
where serial data is shifted in, latched, and then decoded.
Once new data is shifted in, the LOAD line goes high, latch-
ing in the new data. The data is then decoded and the appro-
priate switch is activated to set the desired attenuation level.
This process is continued each and every time an attenua-
tion change is made. When the μPot is powered up, it is
placed into the Mute mode.
μPOT DIGITAL COMPATIBILITY
The μPot’s digital interface section is compatible with TTL or
CMOS logic. The shift register inputs act upon a threshold of
two diode drops above the ground level (Pin 3) or approxi-
mately 1.4V.
TABLE 1. Attenuator Register Set Description
Address Register (Byte 0)
MSB LSB
A7–A0
0000 0000
0000 0001
0000 0010
Data Register (Byte 1)
Contents
MSB LSB
D7–D0
0000 0000
0000 0001
0000 0010
0000 0011
:::::
0001 0000
0001 0001
0001 0010
0001 0011
:::::
0011 1101
0011 1110
0011 1111
0100 0000
:::::
1111 1110
1111 1111
Channel 1
Ignored
Ignored
Attenuation (dB)
0.0
1.0
2.0
3.0
::
16.0
17.0
18.0
19.0
::
61.0
62.0
96 (Mute)
96 (Mute)
::
96 (Mute)
96 (Mute)
DS012353-3
Load and clock falling edges can be coincident, however, the clock falling edge cannot be delayed more than 20 ns from the falling edge of load. It is
*Note:
FIGURE 2. Timing Diagram
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相關(guān)PDF資料
PDF描述
LM1971M LM1971 Overture⑩ Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with/Mute
LM1971N LM1971 Overture⑩ Audio Attenuator Series Digitally Controlled 62 dB Audio Attenuator with/Mute
LM1972 Pot 2-Channel 78dB Audio Attenuator with Mute
LM1972MX Tone/Volume/Balance Control
LM1972M Pot 2-Channel 78dB Audio Attenuator with Mute
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