參數(shù)資料
型號： LM12L454CIV
英文描述： IC-SM-12 BIT DAS
中文描述： 集成電路的Sm - DAS的12位
文件頁數(shù)： 21/36頁
文件大?。?/td> 538K
代理商： LM12L454CIV
2.0 Internal User-Programmable Registers
(Continued)
Bits 12–15
are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the
acquisition mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit
a
sign conversions and two clock
cycles for 8-bit
a
sign conversions or ‘‘watchdog’’ compari-
sons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12–15. Thus, the S/H’s acquisition
time is (9
a
2D) clock cycles for 12-bit
a
sign conversions
and (2
a
2D) clock cycles for 8-bit
a
sign conversions or
‘‘watchdog’’ comparisons, where D is the value stored in
Bits 12–15. The minimum acquisition time compensates for
the typical internal multiplexer series resistance of 2 k
X
,
and any additional delay created by Bits 12–15 compen-
sates for source resistances greater than 80
X
. (For this ac-
quisition time discussion, numbers in ( ) are shown for the
LM12L454/8 operating at 6 MHz. The necessary acquisition
time is determined by the source impedance at the multi-
plexer input. If the source resistance (R
S
)
k
80
X
and the
clock frequency is 6 MHz, the value stored in bits 12–15 (D)
can be 0000. If R
S
l
80
X
, the following equations deter-
mine the value that should be stored in bits 12–15.
D
e
0.45 x R
S
x f
CLK
for 12-bits
a
sign
D
e
0.36 x R
S
x f
CLK
for 8-bits
a
sign and ‘‘watchdog’’
R
S
is in k
X
and f
CLK
is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer be-
tween the signal source and the LM12L458’s multiplexer
inputs. The value of D can also be used to compensate for
the settling or response time of external processing circuits
connected between the LM12L454’s MUXOUT and S/H IN
pins.
Instruction RAM ‘‘01’’
The second Instruction RAM section is selected by placing
a ‘‘01’’ in Bits 8 and 9 of the Configuration register.
Bits 0–7
hold ‘‘watchdog’’
limit
Y
1
. When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to a ‘‘1’’, the LM12L454/8 performs a
‘‘watchdog’’ comparison of the sampled analog input signal
with the limit
Y
1 value first, followed by a comparison of the
same sampled analog input signal with the value found in
limit
Y
2 (Instruction RAM ‘‘10’’).
Bit 8
holds limit
Y
1’s sign.
Bit 9
’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt. A ‘‘1’’ causes a voltage greater than
limit
Y
1 to generate an interrupt, while a ‘‘0’’ causes a volt-
age less than limit
Y
1 to generate an interrupt.
Bits 10–15
are not used.
Instruction RAM ‘‘10’’
The third Instruction RAM section is selected by placing a
‘‘10’’ in Bits 8 and 9 of the Configuration register.
Bits 0–7
hold ‘‘watchdog’’
limit
Y
2
. When Bit 11 of Instruc-
tion RAM ‘‘00’’ is set to a ‘‘1’’, the LM12L454/8 performs a
‘‘watchdog’’ comparison of the sampled analog input signal
with the limit
Y
1 value first (Instruction RAM ‘‘01’’), followed
by a comparison of the same sampled analog input signal
with the value found in limit
Y
2.
Bit 8
holds limit
Y
2’s sign.
Bit 9
’s state determines the limit condition that generates a
‘‘watchdog’’ interrupt. A ‘‘1’’ causes a voltage greater than
limit
Y
2 to generate an interrupt, while a ‘‘0’’ causes a volt-
age less than limit
Y
2 to generate an interrupt.
Bits 10–15
are not used.
2.2 CONFIGURATION REGISTER
The Configuration register, 1000 (A4–A1, BW
e
0) or
1000x (A4–A0, BW
e
1) is a 16-bit control register with
read/write capability. It acts as the LM12L454’s and
LM12L458’s ‘‘control panel’’ holding global information as
well as start/stop, reset, self-calibration, and stand-by com-
mands.
Bit 0
is the START/STOP bit. Reading Bit 0 returns an indi-
cation of the Sequencer’s status. A ‘‘0’’ indicates that the
Sequencer is stopped and waiting to execute the next in-
struction. A ‘‘1’’ shows that the Sequencer is running. Writ-
ing a ‘‘0’’ halts the Sequencer when the current instruction
has finished execution. The next instruction to be executed
is pointed to by the instruction pointer found in the status
register. A ‘‘1’’ restarts the Sequencer with the instruction
currently pointed to by the instruction pointer. (See Bits 8–
10 in the Interrupt Status register.)
Bit 1
is the LM12L454/8’s system RESET bit. Writing a ‘‘1’’
to Bit 1 stops the Sequencer (resetting the Configuration
register’s START/STOP bit), resets the Instruction pointer
to ‘‘000’’ (found in the Interrupt Status register), clears the
Conversion FIFO, and resets all interrupt flags. The RESET
bit will return to ‘‘0’’ after two clock cycles unless it is forced
high by writing a ‘‘1’’ into the Configuration register’s Stand-
by bit. A reset signal is internally generated when power is
first applied to the part. No operation should be started until
the RESET bit is ‘‘0’’.
Writing a ‘‘1’’ to
Bit 2
initiates an auto-zero offset voltage
calibration. Unlike the eight-sample auto-zero calibration
performed during the full calibration procedure, Bit 2 initi-
ates a ‘‘short’’ auto-zero by sampling the offset once and
creating a correction coefficient (full calibration averages
eight samples of the converter offset voltage when creating
a correction coefficient). If the Sequencer is running when
Bit 2 is set to ‘‘1’’, an auto-zero starts immediately after the
conclusion of the currently running instruction. Bit 2 is reset
automatically to a ‘‘0’’ and an interrupt flag (Bit 3, in the
Interrupt Status register) is set at the end of the auto-zero
(76 clock cycles). After completion of an auto-zero calibra-
tion, the Sequencer fetches the next instruction as pointed
to by the Instruction RAM’s pointer and resumes execution.
If the Sequencer is stopped, an auto-zero is performed im-
mediately at the time requested.
Writing a ‘‘1’’ to
Bit 3
initiates a complete calibration pro-
cess that includes a ‘‘long’’ auto-zero offset voltage correc-
tion (this calibration averages eight samples of the compar-
ator offset voltage when creating a correction coefficient)
followed by an ADC linearity calibration. This complete cali-
bration is started after the currently running instruction is
completed if the Sequencer is running when Bit 3 is set to
‘‘1’’. Bit 3 is reset automatically to a ‘‘0’’ and an interrupt flag
(Bit 4, in the Interrupt Status register) will be generated at
the end of the calibration procedure (4944 clock cycles).
After completion of a full auto-zero and linearity calibration,
the Sequencer fetches the next instruction as pointed to by
the Instruction RAM’s pointer and resumes execution. If the
Sequencer is stopped, a full calibration is performed imme-
diately at the time requested.
21
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
LM12L458 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration
LM12L458_06 制造商:NSC 制造商全稱:National Semiconductor 功能描述:12-Bit + Sign Data Acquisition System with Self-Calibration
LM12L458CIV 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
LM12L458CIV/NOPB 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
LM12L458CIVF 制造商:Rochester Electronics LLC 功能描述:12-BIT PARALLEL I/O DAS - Bulk
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