參數(shù)資料
型號(hào): LM1276
廠(chǎng)商: National Semiconductor Corporation
英文描述: 150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs
中文描述: 150 MHz的I2C兼容的RGB前置放大器512個(gè)字符OSD光盤(pán),512個(gè)字符RAM和4 DAC的內(nèi)置
文件頁(yè)數(shù): 39/50頁(yè)
文件大?。?/td> 2597K
代理商: LM1276
Pre-Amplifier Interface Registers
(Continued)
Bit 0
When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not
blanked.
When this bit is a 1, the analog sections of the preamplifier are shut down for low power
consumption. When it is a 0, the analog sections are enabled.
Reserved.
When this bit is set high, the calibration sequence for the PLL Auto Mode is initiated, the PLL Auto
mode is activated, and will unset itself upon completion.
This bit will enable the Burn In Screen.
These bits determine the contrast level of the Burn In Screen.
Bit 1
Bits 3–2
Bit 4
Bit 5
Bits 7–6
Auxiliary Control 1:
AUXCTRL1 (0x843A)
Horizontal Blank Position
HBPOS[4:0]
H. Blank
HBPOS_EN
Reserved
RSV
H Blnk
HBD
Bit 0
When this bit is a 0, the horizontal blanking input at pin 28 is gated to the video outputs to provide
horizontal blanking. When it is a 1, the horizontal blanking at the outputs is disabled.
Reserved.
When this bit is a 1, the position of the Horizontal Blanking pulse can be programmably varied
relative to the horizontal flyback in number of pixels. When this bit is a 0, which is by default, the
horizontal blanking pulse position will not be programmable.
These 5 bits determine the position of the Horizontal Blanking Pulse with respect to the horizontal
flyback in number of pixels.
Bit 1
Bit 2
Bits 7–3
Auxiliary Control 2:
AUXCTRL2 (0x843E)
Clamp
Switch
OSD
CLMP
SW
Res’d
Res’d
Clamp
VBlank
Res’d
Res’d
RSV
RSV
CLMP
OOR
VBL
RSV
RSV
Bits 1–0
Bit 2
Reserved and should be set to zero.
This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video
outputs. When set to a 0, the video outputs do not have vertical blanking.
This is the OSD override bit. This should be set to 0 for normal operation. When set to a 1, the
video outputs are disconnected and OSD only is displayed. This is useful for the OSD display of
special conditions such as “No Signal” and “Input Signal Out of Range”, to avoid seeing
unsynchronized video.
Setting this bit will internally tie the clamp pin to the horizontal sync pin, and the clamp pin will not
require an external input signal.
This is the Clamp Polarity bit. When set to a 0, the LM1276 expects a positive going clamp pulse.
When set to a 1, the expected pulse is negative going.
Reserved and should be set to zero.
Bit 3
Bit 4
Bit 5
Bits 7–6
OSD Tone Transparency:
OSD TRANSP TONE (0x85C0)
OSD TONE
OSDTONE[6:0]
Res’d
RSV
Bits 6–0
Bit 7
These bits determine the transparency level of the OSD background.
Reserved and should be set to zero.
L
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