參數(shù)資料
型號(hào)： LM1270N
廠商： National Semiconductor Corporation
英文描述： Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing
中文描述： 高亮度場(chǎng)致200兆赫與I2C兼容的RGB視頻自動(dòng)上漿圖像增強(qiáng)
文件頁(yè)數(shù)： 25/27頁(yè)
文件大?。?/td> 1302K
代理商： LM1270N
Register Descriptions
(Continued)
Horizontal Window Sync Duration
Register
HW_S0
HW_S1
Addr
2A
2B
7
6
5
4
3
2
1
0
HWS7
HWS6
HWS5
HWS4
HWS3
HWS2
HWS1
HWS9
HWS0
HWS8
This is a 10 bit wide register that records the measured value of the horizontal sync in number of pixels during the vertical blanking
time, providing the STAT bit in D_CNT register is zero.
This register resets to zero after the STAT bit in the D_CNTLS register is read, and not re-enabled until the next vertical sync.Also
note that all six HWINDOW related registers must be read before STAT can reset them to zero in order to prevent updates during
reading.
Horizontal Window Measured Duration
Register
HW_DM0
HW_DM1
Addr
2C
2D
7
6
5
4
3
2
1
0
HWDM7
HWDM6
HWDM5
HWDM4
HWDM3
HWDM2
HWDM10
HWDM1
HWDM9
HWDM0
HWDM8
This is an 11 bit wide register that records the measured value of the duration of the data window on the selected video line in
number of pixels, during any valid data detection period (as set by bit 1 of the register TEST1).
Note:
Only the video detect on the selected WINDOW video line is enabled using the D_CNTL register.
This register resets to zero after the STAT bit in the D_CNTLS register is read, and not re-enabled until the next vertical sync.Also
note that all six HWINDOW related registers must be read before STAT can reset them to zero in order to prevent updates during
reading.
Horizontal Window Data
Register
HW_DAT0
HW_DAT1
HW_DAT2
HW_DAT3
HW_DAT4
HW_DAT5
HW_DAT6
HW_DAT7
HW_DAT8
Addr
2E
2F
30
31
32
33
34
35
36
7
6
5
4
3
2
1
0
HWD07
HWD17
HWD27
HWD37
HWD47
HWD57
HWD67
HWD77
HWD87
HWD06
HWD16
HWD26
HWD36
HWD46
HWD56
HWD66
HWD76
HWD86
HWD05
HWD15
HWD25
HWD35
HWD45
HWD55
HWD65
HWD75
HWD85
HWD04
HWD14
HWD24
HWD34
HWD44
HWD54
HWD64
HWD74
HWD84
HWD03
HWD13
HWD23
HWD33
HWD43
HWD53
HWD63
HWD73
HWD83
HWD02
HWD12
HWD22
HWD32
HWD42
HWD52
HWD62
HWD72
HWD82
HWD01
HWD11
HWD21
HWD31
HWD41
HWD51
HWD61
HWD71
HWD81
HWD00
HWD10
HWD20
HWD30
HWD40
HWD50
HWD60
HWD70
HWD80
Data Control Shadow
Register
D_CNTLS
Addr
37
7
6
5
4
3
2
1
0
STAT
WD
G1
G0
B1
B0
R1
R0
This register is a shadow of the D_CNTL register. Reading this register will cause the STAT bit to reset to 0, which will allow new
data to be transferred into the window and data registers after the next valid data transmission block.
Test Register 0
Register
TEST0
Addr
38
7
6
5
4
3
2
1
0
RSV
RSV
TEE
RSV
RSV
BCE
RSV
RSV
This register is for testing the LM1270 during production. All bits in this register should be set to “0” for proper operation.
Test Register 1
Register
TEST1
Addr
39
7
6
5
4
3
2
1
0
CHGRG
RSV
RDIR
IRPT
AID
BL/INT
LIMIT
INTLC
Bit 0: If this bit is “0” (default), then normal progressive scan mode is enabled. If set to “1”, then interlace mode is enabled.
Bit 1: This bit limits the period during which video data may be detected. If the bit is set to a 1 (default), then the valid data active
period is limited to the vertical blanking time, as set by the vertical blanking register. If a string of 72 clock pulses is received
during this time it is accepted as valid. If a string of 72 pulses is not received until during the active video time, then this
data is ignored.
If the bit is set to “0”, then the first 72 pulse clock string that is detected is considered to be valid, even if this is during the
active video time.
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LM1270NA 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing
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LM1279 制造商:NSC 制造商全稱:National Semiconductor 功能描述:110 MHz RGB Video Amplifier System with OSD
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