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參數(shù)資料
| 型號： | LM1270N |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing |
| 中文描述： | 高亮度場致200兆赫與I2C兼容的RGB視頻自動上漿圖像增強 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大小： | 1302K |
| 代理商： | LM1270N |
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Register Descriptions
(Continued)
This is an 8 bit wide register that records the previous measured value of the vertical sync during video detect in horizontal line
periods from the previous field. It is used when interlace mode is present, in order to accurately determine the correct parameter
value for the frame. Reading this register within less than one complete field period after the Video Detect Reset may give
erroneous results. This register resets to zero after the Video Detect Reset has been written.
Previous Field Vertical Back Porch Duration
Register
V_BP0_PRV
V_BP1_PRV
Addr
25
26
7
6
5
4
3
2
1
0
VBP7
VBP6
VBP5
VBP4
VBP3
VBP2
VBP10
VBP1
VBP9
VBP0
VBP8
This is an 11 bit wide register that records the previous lowest measured value of the vertical back porch during video detect in
horizontal line periods from the previous field. It is used when interlace mode is present, in order to accurately determine the
correct parameter value for the frame. When no video is detected, the sum of this register and the VSYNC should be within 1 line
of the total number of lines per field. Reading this register within less than one complete field period after the Video Detect Reset
may give erroneous results. This register resets to zero after the Video Detect Reset has been written.
Data Control
Register
D_CNTL
Addr
27
7
6
5
4
3
2
1
0
STAT
WD
G1
G0
B1
B0
R1
R0
Bit 5–0: This sets the selection for each video line function when reading data, according to the following table, where X = R, G,
or B:
X1
0
0
1
1
X0
0
1
0
1
Function
Not Selected
Data
Clock
Window
Note that there is nothing to prevent the different bits being set to the same value, resulting in erroneous connection of the video
channels. However, if the registers are wrongly programmed, incorrect information will result. Default is 00.
Bit 6:
This bit enables the Window Detect video detect function to detect the horizontal window line during any valid data
detection period (as set by bit 1 of the register TEST1). Once set it remains set until turned off. When the first string of
72 clock pulses in one line has been detected, the values of the timed horizontal parameters are strobed into the
horizontal window registers, and any further data transfers are ignored until the STAT bit is set to 0 again. (default is 0).
Bit 7:
If the number of clock pulses is exactly 72 when H sync arrives, and the clock pulses occurred during a valid period, as
defined by bit 1 of register TEST1, then the data is parallel loaded in a holding register (HW_DAT) and the STAT bit (bit
7) is set to ‘1’ in the D_CNTL register. This loading only happens if the STAT was initially “0”, otherwise the shift-register
data is discarded. The microcontroller reads the D_CNTL register and if the STAT bit is set, it continues by reading
HW_DAT registers, otherwise the read is discontinued. If the complete block of data registers is read, then at the end
of the data read the microcontroller should read the shadow of D_CNTL in register D_CNTLS, which will clear the STAT
bit.
Alternatively, if only certain data registers need to be read, then either the D_CNTLS register should be read after this
action to clear the STAT bit, or a “0” should be written to bit 7 of this register. Clearing of the STAT bit will then allow
the core to update the HW_DAT registers during the next valid data transmission period.
Horizontal Window Measured Start Duration
Register
HW_SM0
HW_SM1
Addr
28
29
7
6
5
4
3
2
1
0
HWSM7
HWSM6
HWSM5
HWSM4
HWSM3
HWSM2
HWSM10
HWSM1
HWSM9
HWSM0
HWSM8
This is an 11 bit wide register that records the measured value in number of pixels of the duration between the beginning of
HSYNC and the start of the HWINDOW on the video data window line during any valid data detection period (as set by bit 1 of
the register TEST1), providing the STAT bit in D_CNT register is zero.
Note:
Only the video detect on the selected WINDOW video line is enabled using the D_CNTL register. When no video is
detected, this register should return a value of zero. Reading this register during the period between VSYNC and the 72 clock
pulse transmission may give erroneous results. This register resets to zero after the STAT bit in the D_CNTLS register is read,
and not re-enabled until the next vertical sync. Also note that all six HWINDOW related registers must be read before STAT can
reset them to zero in order to prevent updates during reading.
L
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PDF描述 |
|---|---|
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LM1270NA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Hi-Brite 200 MHz I2C Compatible RGB Image Enhancer with Video Auto Sizing |
| LM1276 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs |
| LM1276AAA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 512 Character OSD ROM, 512 Character RAM and 4 DACs |
| LM1279 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:110 MHz RGB Video Amplifier System with OSD |
| LM12791DL WAF | 制造商:Texas Instruments 功能描述: |
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