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參數(shù)資料
| 型號： | LM1253AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 畫面疊加 |
| 英文描述： | Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| 中文描述： | ON-SCREEN DISPLAY IC, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 6/57頁 |
| 文件大?。?/td> | 1621K |
| 代理商： | LM1253AN |
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Brightness/Bias Signal Electrical Characteristics
(See Figure 3 for Test Circuit, and Table 1 for Control Test Settings Chart)
Unless otherwise noted: V
CC
= +5V, V
IN
= 0.7V, C
L
= 8 pF, Video Signal Output = 1 V
PP
, T
A
= 25C, V
ABL
= V
CC
.
Symbol
Parameter
Conditions
LM1253A
Typ
V
REF
0.90
V
REF
10
10
Units
Min
Max
V
BLANK MAX
Maximum Blanking Level
Test Setting 1
V
V
BLANK MIN
t
BLK r
t
BLK f
OS
BLK MAX
Minimum Blanking Level
Blanking Rise Time
Blanking Fall Time
Maximum Rise or Fall Edge
Overshoot
Test Setting 4
Test Setting 1, 10% to 90%,
Test Setting 1, 90% to 10%,
Test Setting 1, 10% to 90% or
90% to 10%, Settling Time Must
be Less Than 50 ns
V
ns
ns
20
%
OSD Electrical Characteristics
(See Figure 3 for Test Circuit)
Unless otherwise noted: V
CC
= +5V, V
IN
= 0.7V, C
L
= 8 pF, Video Signal Output = 1 V
PP
, T
A
= 25C, V
ABL
= V
CC
.
Symbol
Parameter
Conditions
LM1253A
Typ
V
REF
+
0.95
V
REF
+
0.77
V
REF
+
0.59
V
REF
+
0.41
Units
Min
Max
V
OSDHIGH MAX
Maximum OSD Level with OSD
Contrast 11
Palette Set at 111. OSD Contrast
Level 11, Test Setting 3
V
V
OSDHIGH 10
Maximum OSD Level with OSD
Contrast 10
Palette Set at 111. OSD Contrast
Level 10, Test Setting 3
V
V
OSDHIGH 01
Maximum OSD Level with OSD
Contrast 01
Palette Set at 111. OSD Contrast
Level 01, Test Setting 3
V
V
OSDHIGH 00
Maximum OSD Level with OSD
Contrast 00
Palette Set at 111. OSD Contrast
Level 00, Test Setting 3
V
External Interface Signals Electrical Characteristics
(See Figure 3 for Test Circuit)
Unless otherwise noted: V
CC
= +5V, V
IN
= 0.7V, C
L
= 8 pF, Video Signal Output = 1 V
PP
, T
A
= 25C, V
ABL
= V
CC
.
Symbol
Parameter
Conditions
LM1253A
Typ
Units
Min
Max
I
INMAX
Maximum normal forward scan current at
lowest horizontal frequency that input can
withstand
Voltage on H Flyback (Pin 14) which will
Trigger an HBLANK Signal
150
μA
V
HBLANK TRIG
100V H Flyback Signal
through a 100 k
Resistor
0.8
V
I
IN+MAX
Maximum flyback scan current at 125 kHz
that input can withstand
Minimum Flyback Width
Horizontal Period
Minimum Clamp Pulse Width
Maximum Low Level Clamp Pulse Voltage
Minimum High Level Clamp Pulse Voltage
Minimum High Level of Vertical Blank
Output
Maximum Low Level of Vertical Blank
Output
1.5
mA
t
min hflb
t
H
t
PW CLAMP
V
CLAMP L MAX
V
CLAMP H MIN
V
VBLANK HIGH
1
μs
kHz
ns
V
V
20
200
125
1
3
V
VREF BLANK
<
0.75V
V
REF
+ 1
V
V
VBLANK LOW
I
VBLANK OUT
= 100 μA
V
REF
1
V
L
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