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參數(shù)資料
| 型號： | LIS3LV02DQ-TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, PQCC28 |
| 封裝： | 7 X 7 MM, 1.9 MM HEIGHT, PLASTIC, QFN-28 |
| 文件頁數(shù)： | 8/42頁 |
| 文件大?。?/td> | 379K |
| 代理商： | LIS3LV02DQ-TR |
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4 Application Hints
LIS3LV02DQ
16/42
CD00047926
4
Application Hints
Figure 3.
LIS3LV02DQ Electrical Connection
The device core is supplied through Vdd line while the I/O pads are supplied through Vdd_IO
line. Power supply decoupling capacitors (100 nF ceramic, 10
F Al) should be placed as near
as possible to the pin 3 of the device (common design practice).
All the voltage and ground supplies must be present at the same time to have proper behavior
of the IC (refer to Fig. 3). It is possible to remove Vdd mantaining Vdd_IO without blocking the
communication busses.
The functionality of the device and the measured acceleration data is selectable and accessible
through the I2C/SPI interface.When using the I2C, CS must be tied high while SDO must be left
floating. Refer to application note AN2041 for further information on device usage.
4.1
Soldering Information
The QFN-28 package is lead free and green package qualified for soldering heat resistance
according to JEDEC J-STD-020C. Central die pad and pin #1 indicator are physically
connected to GND. Land pattern and soldering recommendations are available upon request.
LIS3LV02DQ
1
7
28
22
21
15
814
DIRECTION OF THE
DETECTABLE
ACCELERATIONS
Vdd_IO
CS
SC
L
/SP
C
S
D
A/
SD
I/
SD
O
SD
O
RD
Y
/I
N
T
10uF
Vdd
Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO
100nF
GND
(TOP VIEW)
Y
1
X
Z
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