參數(shù)資料
型號： LIS35DE
廠商： STMICROELECTRONICS
元件分類： 模擬信號調(diào)理
英文描述： SPECIALTY ANALOG CIRCUIT, PBGA14
封裝： 3 X 5 MM, 0.92 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, LGA-14
文件頁數(shù)： 26/39頁
文件大?。?/td> 650K
代理商： LIS35DE
Register description
LIS35DE
32/39
Doc ID 15594 Rev 1
7.14
FF_WU_SRC_2 (35h)
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_2 register and the FF, WU 2 interrupt and
allows the refreshment of data in the FF_WU_SRC_2 register if the latched option is
chosen.
7.15
FF_WU_THS_2 (36h)
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
Table 40.
FF_WU_SRC_2 (35h) register
X
IA
ZH
ZL
YHYLXHXL
Table 41.
FF_WU_SRC_2 (35h) register description
IA
Interrupt Active. Default value: 0
(0: no interrupt has been generated;
1: one or more interrupt event has been generated)
ZH
Z High. Default value: 0
(0: no interrupt; 1: ZH event has occurred)
ZL
Z Low. Default value: 0
(0: no interrupt; 1: ZL event has occurred)
YH
Y High. Default value: 0
(0: no interrupt; 1: YH event has occurred)
YL
Y Low. Default value: 0
(0: no interrupt; 1: YL event has occurred)
XH
X High. Default value: 0
(0: no interrupt; 1: XH event has occurred)
XL
X Low. Default value: 0
(0: no interrupt; 1: XL event has occurred)
Table 42.
FF_WU_THS_2 (36h) register
DCRM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
Table 43.
FF_WU_THS_2 (36h) register description
DCRM
Resetting mode selection. Default value: 0
(0: counter resetted; 1: counter decremented)
THS6, THS0
Free-fall / wake-up Threshold. Default value: 000 0000
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