參數(shù)資料
型號(hào): LIS302DL
廠商: STMICROELECTRONICS
元件分類: 模擬信號(hào)調(diào)理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC14
封裝: 3 X 5 MM, 0.92 MM HEIGHT, 0.80 MM PITCH, GREEN, PLASTIC, TLGA-14
文件頁數(shù): 25/42頁
文件大小: 602K
代理商: LIS302DL
LIS302DL
Register description
31/42
7.11
FF_WU_SRC_1 (31h)
Free-fall and wake-up source register. Read only register.
Reading at this address clears FF_WU_SRC_1 register and the FF, WU 1 interrupt and
allows the refreshment of data in the FF_WU_SRC_1 register if the latched option was
chosen.
7.12
FF_WU_THS_1 (32h)
Most significant bit (DCRM) is used to select the resetting mode of the duration counter. If
DCRM=0 counter is resetted when the interrupt is no more active else if DCRM=1 duration
counter is decremented.
Table 33.
FF_WU_SRC_1 (31h) register
X
IA
ZH
ZL
YHYLXHXL
Table 34.
FF_WU_SRC_1 (31h) register description
IA
Interrupt active. Default value: 0
(0: no interrupt has been generated; 1: one ore more interrupt has been generated)
ZH
Z high. Default value: 0
(0: no interrupt, 1: ZH event has occurred)
ZL
Z low. Default value: 0
(0: no interrupt; 1: ZL event has occurred)
YH
Y high. Default value: 0
(0: no interrupt, 1: YH event has occurred)
YL
Y low. Default value: 0
(0: no interrupt, 1: YL event has occurred)
XH
X high. Default value: 0
(0: no interrupt, 1: XH event has occurred)
XL
X low. Default value: 0
(0: no interrupt, 1: XL event has occurred)
Table 35.
FF_WU_THS_1 (32h) register
DCRM
THS6
THS5
THS4
THS3
THS2
THS1
THS0
Table 36.
FF_WU_THS_1 (32h) register description
DCRM
Resetting mode selection. Default value: 0
(0: counter resetted; 1: counter decremented)
THS6, THS0
Free-fall / wake-up threshold: default value: 000 000x
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