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參數(shù)資料
| 型號： | LH7A400N0G000B5 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 32-Bit System-on-Chip |
| 封裝： | LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT |
| 文件頁數(shù)： | 33/65頁 |
| 文件大?。?/td> | 834K |
| 代理商： | LH7A400N0G000B5 |
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32-Bit System-on-Chip
LH7A400
Preliminary data sheet
Rev. 01
—
16 July 2007
33
NXP Semiconductors
Power Supply Sequencing
NXP recommends that the 1.8 V power supply be
energized before the 3.3 V supply. If this is not possi-
ble, the 1.8 V supply may not lag the 3.3 V supply by
more than 100
μ
s. If longer delay time is needed, it is
recommended that the voltage difference between the
two power supplies be within 1.5 V during power supply
ramp up.
To avoid a potential latchup condition, voltage
should be applied to input pins only after the device is
powered-on as described above.
AC Specifications
All signals described in Table 12 relate to transi-
tions after a reference clock signal. The illustration in
Figure 9 represents all cases of these sets of mea-
surement parameters.
The reference clock signals in this design are:
HCLK, internal System Bus clock (‘C’ in timing data)
PCLK, Peripheral Bus clock
SSPCLK, Synchronous Serial Port clock
UARTCLK, UART Interface clock
LCDDCLK, LCD Data clock from the
LCD Controller
ACBITCLK, AC97 clock
SCLK, Synchronous Memory clock.
All signal transitions are measured at the 50 % point.
For outputs from the LH7A400, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from a valid address bus, or rising edge of the
peripheral clock. Maximum requirements for tOVXXX
are shown in Table 12.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the valid
address bus, or rising edge of the peripheral clock. Min-
imum requirements for tOHXXX are listed in Table 12.
For Inputs, tISXXX (e.g. tISD) represents the amount
of time the input signal must be valid before a valid
address bus, or rising edge of the peripheral clock
(except SSP and ACI). Maximum requirements for
tISXXX are shown in Table 12.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
valid address bus, or rising edge of the peripheral clock
(except SSP and ACI). Minimum requirements are
shown in Table 12.
Figure 9. LH7A400 Signal Timing
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
7A400-28
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH7A400N0G000B5,55 | 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A400N0G000B5,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A400N0G000B5;55 | 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A400N0G000B5-S | 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A400N0W000 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32-Bit System-on-Chip |
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