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參數(shù)資料
| 型號： | LH7A400N0G000B5 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | 32-Bit System-on-Chip |
| 封裝： | LH7A400N0F000B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT1020-1.html<1<Always Pb-free,;LH7A400N0F076B5<SOT1020-1 (LFBGA256)|<<http://www.nxp.com/packages/SOT |
| 文件頁數(shù)： | 28/65頁 |
| 文件大小： | 834K |
| 代理商： | LH7A400N0G000B5 |
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LH7A400
32-Bit System-on-Chip
28
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
Real Time Clock (RTC)
The RTC can be used to provide a basic alarm func-
tion or long time-base counter. This is achieved by gen-
erating an interrupt signal after counting for a
programmed number of cycles of a real-time clock
input. Counting in one second intervals is achieved by
use of a 1 Hz clock input to the RTC.
Battery Monitor Interface (BMI)
The LH7A400 BMI is a serial communication inter-
face specified for two types of Battery Monitors/Gas
Gauges. The first type employs a single wire interface.
The second interface employs a two-wire multi-master
bus, the Smart Battery System Specification. If both
interfaces are enabled at the same time, the Single
Wire Interface will have priority. A brief overview of
these two interface types are given here.
SINGLE WIRE INTERFACE
The Single Wire Interface performs:
Serial-to-parallel conversion on data received from
the peripheral device
Parallel-to-serial conversion on data transmitted to
the peripheral device
Data packet coding/decoding on data transfers
(incorporating Start/Data/Stop data packets)
The Single Wire interface uses a command-based
protocol, in which the host initiates a data transfer by
sending a WriteData/Command word to the Battery
Monitor. This word will always contain the Command
section, which tells the Single Wire Interface device the
location for the current transaction. The most signifi-
cant bit of the Command determines if the transaction
is Read or Write. In the case of a Write transaction,
then the word will also contain a WriteData section with
the data to be written to the peripheral.
SMART BATTERY INTERFACE
The SMBus Interface performs:
Serial-to-Parallel conversion on data received from
the peripheral device
Parallel-to-Serial conversion of data transmitted to
the peripheral device.
The Smart Battery Interface uses a two-wire multi-
master bus (the SMBus), meaning that more than one
device capable of controlling the bus can be connected
to it. A master device initiates a bus transfer and provides
the clock signals. A slave device can receive data pro-
vided by the master or it can provide data to the master.
Since more than one device may attempt to take control
of the bus as a master, SMBus provides an arbitration
mechanism, by relying on the wired-AND connection of
all SMBus interfaces to the SMBus.
DC-to-DC Converter
The features of the DC-DC Converter interface are:
Dual drive PWM outputs, with independent closed
loop feedback
Software programmable configuration of one of 8
output frequencies (each being a fixed divide of the
input clock).
Software programmable configuration of duty cycle
from 0 to 15/16, in intervals of 1/16.
Output polarity (for positive or negative voltage gen-
eration) is hardware-configured during power-on
reset via the polarity select inputs
Each PWM output can be dynamically switched to
one of a pair of preprogrammed frequency/duty
cycle combinations via external pins.
Watchdog Timer (WDT)
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer that is
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The WDT features are:
Driven by the system clock
16 programmable time-out periods: 2
16
through 2
31
clock cycles
Generates a system reset (resets LH7A400) or a
FIQ Interrupt whenever a time-out period is reached
Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
Protection mechanism guards against
interrupt-service-failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a System Reset.
General Purpose I/O (GPIO)
The LH7A400 GPIO has eight ports, each with a
data register and a data direction register. It also has
added registers including Keyboard Scan, PINMUX,
GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and
PGHCON.
The data direction register determines whether a
port is configured as an input or an output while the
data register is used to read the value of the GPIO pins.
The GPIO Interrupt Enable, INTYPE1/2, and GPI-
OFEOI registers are used to control edge-triggered
Interrupts on Port F. The PINMUX register controls
what signals are output of Port D and Port E when they
are set as outputs, while the PGHCON controls the
operations of Port G and H.
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| LH7A400N0G000B5,55 | 功能描述:ARM微控制器 - MCU LCD,USB FS/HOST,MMU,ADC,BGA324 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A400N0G000B5,551 | 制造商:NXP Semiconductors 功能描述: |
| LH7A400N0G000B5;55 | 功能描述:ARM微控制器 - MCU LCD USB FS/HOST MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A400N0G000B5-S | 功能描述:ARM微控制器 - MCU ARM9 LCD USB HOST RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH7A400N0W000 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32-Bit System-on-Chip |
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