參數(shù)資料
型號(hào)： LH79525N0Q100A1
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： System-on-Chip
封裝： LH79524N0F100A1<SOT1019-1 (LFBGA208)|<<http://www.nxp.com/packages/SOT1019-1.html<1<Always Pb-free,;LH79525N0Q100A1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1
文件頁(yè)數(shù)： 26/64頁(yè)
文件大?。?/td> 970K
代理商： LH79525N0Q100A1
LH79524/LH79525
System-on-Chip
26
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
Ethernet MAC Controller
The on-board Ethernet MAC Controller (EMAC) is
compatible with IEEE 802.3, and has passed the Uni-
versity of New Hampshire (UNH) testing. It supports
both 10- and 100-Mbit/s, and full and half duplex oper-
ation. Other features include:
Statistics counter registers for RMON/MIB
MII interface to the physical layer
Interrupt generation to signal receive and transmit
completion
Transmit and receive FIFOs
Automatic pad and CRC generation on transmitted
frames
Automatic discard of frames received with errors
Address checking logic supports up to four specific
(hardware) 48-bit addresses
Supports promiscuous mode where all valid
received frames are copied to memory
Hash matching of unicast and multicast destination
addresses
Supports physical layer management through MDIO
interface
Supports serial network interface operation
Support for:
– Half duplex flow control by forcing collisions on in-
coming frames
– Full duplex flow control with recognition of incom-
ing pause frames and hardware generation of
transmitted pause frames
– 802.Q VLAN tagging with recognition of incoming
VLAN and priority tagged frames
Multiple buffers per receive and transmit frame
Software configures the MAC address
Jumbo frames of up to 10,240 bytes supported.
I
2
C Controller
The I
2
C Controller includes a two-wire I
2
C serial
interface capable of operating in either Master or Slave
mode. The block conforms to the I
2
C 2.1 Bus Specifi-
cation for data rates up to 400 kbit/s. The two wires are
SCL (serial clock) and SDA (serial data). The I
2
C mod-
ule provides the following features:
Two-wire synchronous serial interface
Operates in both the standard mode, for data rates
up to 100 kbit/s, and the fast mode, with data rates
up to 400 kbit/s
Communicates with devices in the fast mode as well
as the standard mode if both are attached to the bus.
SSP To I
2
S Converter
The SSP to I
2
S converter is an interface that con-
verts a synchronous serial communication stream in TI
DSP-compatible mode into an I
2
S compliant synchro-
nous serial stream. The I
2
S converter operates on
serial data in both master and slave mode.
The I
2
S converter provides:
Programmable Word Select (WS) delay
Left/right channel information:
– Current WS value at the pin
– WS value associated with next entry written to
TX FIFO
– WS value associated with next entry read from
RX FIFO
Ability to invert WS state
Ability to invert the bit clock
Supports frame size of 16 bits only. Any other frame
size will result in a frame size error. Each frame
transmits starting with the most-significant bit.
Master and slave modes supported
As with the SSP, a single combined interrupt is gen-
erated as an OR function of the individual interrupt
requests. This interrupt replaces the SSP interrupt,
which is used solely as an input to the I
2
S converter.
Additional interrupts:
– Transmit FIFO underrun
– Transmit frame size error
– Receive frame size error
A set of Interrupt registers contain all the information
in the SSPIMSC, SSPRIS, and SSPMIS registers,
plus the transmit underrun error and frame size errors
Additional status bits:
– Transmit FIFO Full
– Receive FIFO Empty
Passes SSP data unaltered when module is not
enabled
Loopback Test Mode support.
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