參數(shù)資料
型號(hào)： LH79525N0Q100A1
廠商： NXP Semiconductors N.V.
元件分類： 數(shù)學(xué)處理器
英文描述： System-on-Chip
封裝： LH79524N0F100A1<SOT1019-1 (LFBGA208)|<<http://www.nxp.com/packages/SOT1019-1.html<1<Always Pb-free,;LH79525N0Q100A1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1
文件頁(yè)數(shù)： 25/64頁(yè)
文件大?。?/td> 970K
代理商： LH79525N0Q100A1
System-on-Chip
LH79524/LH79525
Preliminary data sheet
Rev. 01
—
16 July 2007
25
NXP Semiconductors
Watchdog Timer
The Watchdog Timer provides hardware protection
against malfunctions. It is a programmable timer to be
reset by software at regular intervals. Failure to reset
the timer will cause a FIQ interrupt. Failure to service
the FIQ interrupt will then generate a System Reset.
The features of the Watchdog Timer are:
Driven by the bus clock
16 programmable time-out periods: 2
16
through 2
31
clock cycles
Generates a reset or an FIQ Interrupt whenever a
time-out period is reached
Software enable, lockout, and counter-reset mecha-
nisms add security against inadvertent writes
Protection mechanism guards against interrupt-ser-
vice failure:
– The first WDT time-out triggers FIQ and asserts
nWDFIQ status flag
– If FIQ service routine fails to clear nWDFIQ, then
the next WDT time-out triggers a system reset.
Timers
The LH79524 and LH79525 incorporate three 16-bit
independently programmable Timer modules. The tim-
ers are clocked by the system clock, but have an inter-
nal scaled-down system clock that is used for the Pulse
Width Modulator (PWM) and compare functions.
All counters are incremented by an internal pre-
scaled counter clock or external clock and can gener-
ate an overflow interrupt. All three timers have separate
internal prescaled counter clocks, with either a com-
mon external clock or a prescaled version of the sys-
tem clock.
Timer 0 has five Capture Registers and two Com-
pare Registers.
Timer 1 and Timer 2 have two Capture and two Com-
pare Registers each.
The Capture Registers have edge-selectable inputs
and can generate an interrupt. The Compare Registers
can force the compare output pin either HIGH or LOW
upon a match.
The timers support a PWM Mode that uses the two
Timer Compare Registers associated with a timer to
create a PWM. Each timer can generate a separate
interrupt. The interrupt becomes active if any enabled
compare, capture, or overflow interrupt condition
occurs. The interrupt remains active until all compare,
capture, and overflow interrupts are cleared.
General Purpose Input/Output (GPIO)
The LH79524 provides up to 108 bits of programma-
ble input/output, and the LH79525 provides 86 bits.
Many of the GPIO pins are multiplexed with other sig-
nals. All GPIO feature:
Individually programmable input/output pins
All default to Input on power-up.
LH79524
– Ports A-I, K, L, and N: Bidirectional I/O (Port N is
4 bits wide)
– Port J: Input only
– Port M: Output only
LH79525
– Ports A-I: Bidirectional I/O
– Port J: Input only
– Port M: Output only (6 bits wide)
Boot Controller
The boot controller allows selection of the hardware
device to be used for booting.
Supports booting from 8-, 16-, or 32-bit devices,
selectable via external pins at power-on reset
Configures the byte lane boot state for nCS1,
selectable via external pins at power-on reset.
Supports booting from alternate external devices
(e.g., NAND flash) via external pins on power-on reset
Glueless interface to external NAND flash.
USB Device
The USB Device integrated into the LH79524/
LH79525 is compliant with the USB 1.1 and 2.0 speci-
fication, and compatible with both the OpenHCI and
Intel UHCI standards. The USB Device:
Supports Full-Speed (12 Mbit/s) operation, and
suspend and resume signaling
Four Endpoints
Bulk/Interrupt or Isochronous Transfers
FIFO for each Endpoint direction (except EP0 which
shares a FIFO between IN/OUT). FIFOs exist in
2464 × 8 RAM
Supports DMA accesses to FIFO.
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