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參數(shù)資料
| 型號： | LH79524N0F100A1 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學處理器 |
| 英文描述： | System-on-Chip |
| 封裝： | LH79524N0F100A1<SOT1019-1 (LFBGA208)|<<http://www.nxp.com/packages/SOT1019-1.html<1<Always Pb-free,;LH79525N0Q100A1<SOT1017-1 (LQFP176)|<<http://www.nxp.com/packages/SOT1 |
| 文件頁數(shù)： | 29/64頁 |
| 文件大小： | 970K |
| 代理商： | LH79524N0F100A1 |
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System-on-Chip
LH79524/LH79525
Preliminary data sheet
Rev. 01
—
16 July 2007
29
NXP Semiconductors
AC Test Conditions
Power Consumption By Peripheral Device
Table 13 shows the typical power consumption by
individual peripheral device.
AC Specifications
All signals described in Table 14 relate to transitions
after a reference clock signal. The illustration in Figure
9 represents all cases of these sets of measurement
parameters; except for the Asynchronous Memory
Interface — which are referenced to Address Valid.
The reference clock signals in this design are:
HCLK, the System Bus clock
PCLK, the Peripheral Bus clock (locked to HCLK in
the LH79524/LH79525)
SSPCLK, the Synchronous Serial Interface clock
UARTCLK, the UART Interface clock
LCDDCLK, the LCD Data clock from the
LCD Controller
and SDCLK, the SDRAM clock.
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal. See
Figure 9.
For outputs from the LH79524/LH79525, tOVXXX
(e.g. tOVA) represents the amount of time for the out-
put to become valid from the rising edge of the refer-
ence clock signal. Maximum requirements for tOVXXX
are shown in Table 14.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 14.
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 14.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
rising edge of the reference clock signal. Minimum
requirements are shown in Table 14.
PARAMETER
RATING
UNIT
Supply Voltage (VDD)
Core Voltage (VDDC)
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing
Reference Levels
3.0 to 3.6
1.7 to 1.9
VSS to VDD
2
V
V
V
ns
VDD/2
V
Table 13. Peripheral Current Consumption
PERIPHERAL
TYPICAL
UNITS
μ
A
μ
A
mA
μ
A
μ
A
mA
μ
A
μ
A
μ
A
ADC/TSC
Counter/Timers
DMA
Ethernet Controller
I
2
S
LCD Controller
RTC
SSP
590
203
4.2
670
200
2.2
5.1
508
UARTs
203
USB Device (+PLL)
5.6 (+3.3)
mA
Figure 9. LH79524/LH79525 Signal Timing
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
LH79525-28
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LH79524N0F100A1,55 | 功能描述:ARM微控制器 - MCU LCD,USB,ETH’NET,MMU,ADC,BGA208 RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH79524N0F100A1,551 | 制造商:NXP Semiconductors 功能描述: |
| LH79524N0F100A1;55 | 功能描述:ARM微控制器 - MCU LCD USB ETH’NET MMU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH79524N0F100A1-S | 功能描述:ARM微控制器 - MCU ARM7 LCD MMU ENET RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風格:SMD/SMT |
| LH79525 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:System-on-Chip |
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