
LH75401/LH75411
System-on-Chip
26
Rev. 01
—
16 July 2007
Preliminary data sheet
NXP Semiconductors
Static Random Access Memory Controller
The LH75401/LH75411 microcontrollers have 32 kB
of Static Random Access Memory (SRAM) organized
into two 16 kB blocks:
16 kB of TCM 0 Wait State SRAM is available to the
processor as an ARM7TDMI-S bus slave.
16 kB of internal SRAM is available as an AHB slave
and accessible via processor, DMAC, and LCDC.
Each memory segment is 512 MB, though the TCM
and internal SRAMs are 16 kB each in size. Any
access beyond the first 16 kB is mapped to the lower
16 kB, but does not cause a data or prefetch abort.
Static Memory Controller (SMC)
The Static Memory Controller (SMC) is an AMBA
AHB slave peripheral that provides the interface
between the LH75401/LH75411 microcontrollers and
external memory devices.
SMC FEATURES
Provides four banks of external memory, each with a
maximum size of 16 MB.
Supports
Random Access Memory (RAM), Read Only
Memory (ROM), Flash, and burst ROM
Supports external bus and external device widths of
8 and 16 bits
Supports Asynchronous Burst Mode read access for
Burst Mode ROM devices, with up to 32 independent
wait states for read and write accesses
Supports indefinite extended wait states via an
external hardware pin (nWAIT)
Supports varied bus turnaround cycles (1 to 16)
between a read and write operation
memory-mapped
devices,
including
Direct Memory Access Controller (DMAC)
One central DMAC services all peripheral DMA
requirements for the DMA-capable peripherals listed in
Table 9.
The DMA is controlled by the system clock. It has an
APB slave port for programming of its registers and an
AHB port for data transfers.
DMAC FEATURES
Four data streams that can be used to service:
– Four peripheral data streams (peripheral-to-
memory or memory-to-peripheral)
– Three peripheral data streams and one memory-
to-memory data stream.
Three transfer modes:
– Memory to Memory (selectable on Stream3)
– Peripheral to Memory (all streams)
– Memory to Peripheral (all streams).
Built-in data stream arbiter
Seven programmable registers for each stream
Ability for each stream to indicate a transfer error via
an interrupt
16-word First-In, First Out (FIFO) array, with pack
and unpack logic to handle all input/output combina-
tions of byte, half-word, and word transfers
APB slave port allows the ARM core to program
DMAC registers
AHB port for data transfers.
Table 8. APB Peripheral Register Mapping
ADDRESS RANGE
DEVICE
0xFFFC0000 - 0xFFFC0FFF UART0 (16550)
0xFFFC1000 - 0xFFFC1FFF UART1 (16550)
0xFFFC2000 - 0xFFFC2FFF UART2 (82510)
0xFFFC3000 - 0xFFFC3FFF Analog-to-Digital Converter
0xFFFC4000 - 0xFFFC4FFF Timer Module
0xFFFC5000 - 0xFFFC5FFFReserved (LH75411)
0xFFFC6000 - 0xFFFC6FFF Synchronous Serial Port
0xFFFC7000 - 0xFFFDAFFF Reserved
0xFFFDB000 - 0xFFFDBFFF GPIO4
0xFFFDC000 - 0xFFFDCFFF GPIO3
0xFFFDD000 - 0xFFFDDFFF GPIO2
0xFFFDE000 - 0xFFFDEFFF GPIO1
0xFFFDF000 - 0xFFFDFFFF GPIO0
0xFFFE0000 - 0xFFFE0FFF Real Time Clock
0xFFFE1000 - 0xFFFE1FFF DMAC
0xFFFE2000 - 0xFFFE2FFFController
0xFFFE3000 - 0xFFFE3FFF Watchdog Timer
0xFFFE4000 - 0xFFFE4FFF Advanced LCD Interface
0xFFFE5000 - 0xFFFE5FFF I/O Configuration Peripheral
0xFFFE6000 - 0xFFFEFFFF Reserved
Table 9. DMAC Stream Assignments
DMA REQUEST SOURCE
DMA STREAM
UART1RX (highest priority)
Stream0
UART1TX
Stream1
UART0RX/External Request (DREQ)
Stream2
UART0TX (lowest priority)
Stream3