參數(shù)資料
型號: LH75401N0Q100C0
廠商: NXP Semiconductors N.V.
元件分類: 數(shù)學(xué)處理器
英文描述: System-on-Chip
封裝: LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1
文件頁數(shù): 31/63頁
文件大?。?/td> 665K
代理商: LH75401N0Q100C0
System-on-Chip
LH75401/LH75411
Preliminary data sheet
Rev. 01
16 July 2007
31
NXP Semiconductors
Vectored Interrupt Controller (VIC)
All internal and external interrupts are routed to the
VIC, where hardware determines the interrupt priority
(see Table 11). The VIC is also where the appropriate
signal to the processor (IRQ or FIQ) is generated. The
processor services the interrupt as either a vectored
interrupt or a default-vectored interrupt.
The VIC accepts inputs from 32 interrupt source lines:
Seven external
Twenty-three internal
Two used as software interrupts.
All 32 interrupt source lines can be enabled, disabled,
and cleared individually, and individual status can be
determined. On reset, all interrupts are disabled.
The VIC also accepts software-generated interrupts.
Software-generated interrupts use the same enabling
control as hardware-generated interrupts.
The VIC provides 32 interrupts:
16 vectored interrupts
16 or more default-vectored interrupts.
Any of the 32 interrupt source lines can be assigned
to any of the 16 interrupt vectors. Any line not explicitly
assigned to an interrupt vector is processed as a
default-vectored interrupt. At reset, all 32 lines become
default-vectored interrupts.
Each interrupt line can be explicitly identified as an
IRQ (default) or FIQ interrupt. Vectored-interrupt
servicing is only available for IRQ interrupts.
Table 11. Interrupt Channels
POSITION
DESCRIPTION
SOURCE
0
1
2
3
4
5
6
7
8
9
WDT
Not Used
ARM7 DBGCOMMRX
ARM7 DBGCOMMTX
Timer0 Combined
Timer1 Combined
Timer2 Combined
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
Not Used
RTC_ALARM
ADC TSCIRQ (combined)
ADC BrownOutINTR
ADC PenIRQ
LCD
SSPTXINTR
SSPRXINTR
SSPRORINTR
SSPRXTOINTR
SSPINTR
UART1 UARTRXINTR
UART1 UARTTXINTR
UART1 UARTINTR
UART0 UARTINTR
UART2 Interrupt
DMA
Watchdog Timer
Available as a software interrupt
Sourced by the ARM7TDMI-S Core
Sourced by the ARM7TDMI-S Core
Timer0
Timer1
Timer2
Sourced by the GPIO Block
Sourced by the GPIO Block
Sourced by the GPIO Block
Sourced by the GPIO Block
Sourced by the GPIO Block
Sourced by the GPIO Block
Sourced by the GPIO Block
Available as a software interrupt
Real Time Clock
Analog-to-Digital Converter
Brown Out Detector
Analog-to-Digital Converter
LCD Controller
Synchronous Serial Port
Synchronous Serial Port
Synchronous Serial Port
Synchronous Serial Port
Synchronous Serial Port
UART1
UART1
UART1
UART0
UART2
DMA
CAN (LH75401)
Reserved (LH75411)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
CAN
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