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參數(shù)資料
| 型號(hào)： | LH75401N0Q100C0 |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 數(shù)學(xué)處理器 |
| 英文描述： | System-on-Chip |
| 封裝： | LH75401N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1.html<1<Always Pb-free,;LH75411N0Q100C0<SOT486-1 (LQFP144)|<<http://www.nxp.com/packages/SOT486-1 |
| 文件頁數(shù)： | 25/63頁 |
| 文件大?。?/td> | 665K |
| 代理商： | LH75401N0Q100C0 |
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System-on-Chip
LH75401/LH75411
Preliminary data sheet
Rev. 01
—
16 July 2007
25
NXP Semiconductors
Reset Generation
EXTERNAL RESETS
Two external signals generate resets to the
ARM7TDMI-S core:
nPOR sets all internal registers to their default state
when asserted. It is used as a Power-On Reset.
nRESETIN sets all internal registers, except the
JTAG circuitry, to their default state when asserted.
When nPOR is asserted, nRESETIN defines the
microcontroller Test Mode. When nPOR is released,
nRESETIN behaves during Reset as described
previously.
INTERNAL RESETS
There are two types of Internal Resets generated:
System Reset
RTC Reset.
System and RTC Resets are asserted by:
An External Reset (a logic LOW signal on the exter-
nal nRESETIN or nPOR input pin)
A signal from the internal Watchdog Timer
A Soft Reset.
The reset latency depends on the PLL lock state.
AHB Master Priority and Arbitration
The LH75401/LH75411 microcontrollers have three
AHB masters:
ARM processor
DMAC
LCD Controller.
Each AHB master has a priority level that is perma-
nent and cannot change.
Memory Interface Architecture
The LH75401/LH75411 microcontrollers provide the
following data-path management resources on chip:
AHB and APB data buses
16 kB of zero-wait-state TCM SRAM accessible via
processor
16 kB of internal SRAM accessible via processor,
DMAC, and LCDC
A Static Memory Controller (SMC) that controls
access to external memory
A 4-stream general-purpose DMAC.
All external and internal system resources are
memory-mapped. This memory map partition has three
views, based on the setting of the REMAP bits in the
Reset, Clock, and Power Controller (RCPC).
The second partitioning of memory space is the
dividing of the segments into sections. The external
memory segment is divided into eight 64 MB sections,
of which the first four are used, each having a chip
select associated with it. Access to any of the last four
sections does not result in an external bus access and
does not cause a memory abort. The peripheral regis-
ter segment is divided into 4 kB peripheral sections, 21
of which are assigned to peripherals.
Table 6. Bus Master Priority
PRIORITY
BUS MASTER PRIORITY
1 (Highest)
Color LCDC (LH75401 and LH75411)
2
DMAC
3 (Lowest)
ARM7TDMI-S Core (Default)
Table 7. Memory Mapping
ADDRESS
REMAP = 00
(DEFAULT)
REMAP = 01 REMAP = 10
0x00000000
External
Memory
Internal
SRAM
TCM SRAM
0x20000000
Reserved
Reserved
Reserved
0x40000000
External
Memory
External
Memory
External
Memory
0x60000000
Internal
SRAM
Internal
SRAM
Internal
SRAM
0x80000000
TCM SRAM
TCM SRAM
TCM SRAM
0xA0000000
Reserved
Reserved
Reserved
0xC0000000
Reserved
Reserved
Reserved
0xE0000000 -
0xFFFBFFFF
Reserved
Reserved
Reserved
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LH75401N0Q100C0,55 | 功能描述:ARM微控制器 - MCU ARM7 CAN LCD ADC RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:72 MHz 程序存儲(chǔ)器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT |
| LH75401N0Q100C055 | 制造商:NXP Semiconductors 功能描述:MCU ARM7 BLUESTREAK 144LQFP |
| LH75401N0Q100C055 | 制造商:NXP Semiconductors 功能描述:IC 32BIT MCU 84MHZ LQFP-144 |
| LH75401N0Q100C0551 | 制造商:Rochester Electronics LLC 功能描述: 制造商:NXP 功能描述: 制造商:NXP Semiconductors 功能描述: |
| LH75401N0Q100C0-S | 制造商:NXP Semiconductors 功能描述:SOC Microcontroller 1.98V 144-Pin LQFP Tray |
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