鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LFXP20E-3F256I
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 63/397闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 19.7KLUTS 188I/O 256-BGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� XP
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 20000
RAM 浣嶇附瑷堬細 405504
杓稿叆/杓稿嚭鏁�(sh霉)锛� 188
闆绘簮闆诲锛� 1.14 V ~ 1.26 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 256-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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LatticeECP/EC and LatticeXP
Lattice Semiconductor
sysIO Usage Guide
8-15
Appendix A. HDL Attributes for Synplify
and Precision RTL Synthesis
Using these HDL attributes, you can assign sysIO attributes directly in your source. You will need to use the attri-
bute definition and syntax for the synthesis vendor you are planning to use. Below are a list of all the sysIO attri-
butes syntax and examples for Precision RTL Synthesis and Synplify. This section only lists the sysIO buffer
attributes for these devices. You can refer to the Precision RTL Synthesis and Synplify user manuals for a complete
list of synthesis attributes. These manuals are available through ispLEVER Software Help.
VHDL Synplify/Precision RTL Synthesis
This section lists syntax and examples for all the sysIO attributes in VHDL when using Precision RTL Synthesis or
Synplicity synthesis tools.
Syntax
Table 8-8. VHDL Attribute Syntax for Synplify and Precision RTL Synthesis
Examples
IO_TYPE
--***Attribute Declaration***
ATTRIBUTE IO_TYPE: string;
--***IO_TYPE assignment for I/O Pin***
ATTRIBUTE IO_TYPE OF portA:
SIGNAL IS 鈥淧CI33鈥�;
ATTRIBUTE IO_TYPE OF portB:
SIGNAL IS 鈥淟VCMOS33鈥�;
ATTRIBUTE IO_TYPE OF portC:
SIGNAL IS 鈥淟VDS25鈥�;
Attribute
Syntax
IO_TYPE
attribute IO_TYPE: string;
attribute IO_TYPE of Pinname: signal is 鈥淚O_TYPE Value鈥�;
OPENDRAIN
attribute OPENDRAIN: string;
attribute OPENDRAIN of Pinname: signal is 鈥淥penDrain Value鈥�;
DRIVE
attribute DRIVE: string;
attribute DRIVE of Pinname: signal is 鈥淒rive Value鈥�;
PULLMODE
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is 鈥淧ullmode Value鈥�;
PCICLAMP
attribute PCICLAMP: string;
attribute PCICLAMP of Pinname: signal is 鈥淧CIClamp Value鈥�;
SLEWRATE
attribute PULLMODE: string;
attribute PULLMODE of Pinname: signal is 鈥淪lewrate Value鈥�;
FIXEDDELAY
attribute FIXEDDELAY: string;
attribute FIXEDDELAY of Pinname: signal is 鈥淔ixeddelay Value鈥�;
DIN
attribute DIN: string; attribute DIN of Pinname: signal is 鈥� 鈥�;
DOUT
attribute DOUT: string; attribute DOUT of Pinname: signal is 鈥� 鈥�;
LOC
attribute LOC: string; attribute LOC of Pinname: signal is 鈥減in_locations鈥�;
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
LFXP20C-4F256C IC FPGA 19.7KLUTS 188I/O 256-BGA
ACC40DRTN-S93 CONN EDGECARD 80POS DIP .100 SLD
MIC5333-PPYMT TR IC REG LDO 3V .3A 10TMLF
ISL9003AIEJZ-T IC REG LDO 2.8V .15A SC70-5
AS1363-BSTT-15 IC REG LDO 1.5V .5A SOT23-6
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LFXP20E-3F484C 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 340 IO 1. 2V -3 Spd RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
LFXP20E-3F484I 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 340 IO 1. 2V -3 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
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