1 (Cont.)
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� LFXP20E-3F256I
寤犲晢锛� Lattice Semiconductor Corporation
鏂囦欢闋佹暩(sh霉)锛� 369/397闋�
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC FPGA 19.7KLUTS 188I/O 256-BGA
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 90
绯诲垪锛� XP
閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� 20000
RAM 浣嶇附瑷�(j矛)锛� 405504
杓稿叆/杓稿嚭鏁�(sh霉)锛� 188
闆绘簮闆诲锛� 1.14 V ~ 1.26 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� -40°C ~ 100°C
灏佽/澶栨锛� 256-BGA
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 256-FPBGA锛�17x17锛�
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4-5
Pinout Information
Lattice Semiconductor
LatticeXP Family Data Sheet
Pin Information Summary
1 (Cont.)
XP10
XP15
XP20
Pin Type
256 fpBGA 388 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA 256 fpBGA 388 fpBGA 484 fpBGA
Single Ended User I/O
188
244
188
268
300
188
268
340
Differential Pair User I/O
2
76
104
76
112
128
76
112
144
Configuration
Dedicated
1111111111111111
Muxed
1414141414141414
TAP
5
555
5
Dedicated
(total without supplies)
6
666
6
VCC
814814
28814
28
VCCAUX
4
444
12
44
12
VCCPLL
2
222
2
VCCIO
Bank0
2
525
425
4
Bank1
2
525
425
4
Bank2
2
424
4
Bank3
2
424
4
Bank4
2
525
425
4
Bank5
2
525
425
4
Bank6
2
424
4
Bank7
2
424
4
GND
2450245056245056
GNDPLL
2
222
2
NC
0240
0400
0
Single Ended/
Differential I/O
per Bank
2
Bank0
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank1
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank2
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank3
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank4
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank5
26/11
33/14
26/11
39/16
40/17
26/11
39/16
47/20
Bank6
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
Bank7
21/8
28/12
21/8
28/12
35/15
21/8
28/12
38/16
VCCJ
1
111
1
1. During configuration the user-programmable I/Os are tri-stated with an internal pull-up resistor enabled. If any pin is not used (or not bonded
to a package pin), it is also tri-stated with an internal pull-up resistor enabled after configuration.
2. The differential I/O per bank includes both dedicated LVDS and emulated LVDS pin pairs. Please see the Logic Signal Connections table for
more information.
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
LFXP20C-4F256C IC FPGA 19.7KLUTS 188I/O 256-BGA
ACC40DRTN-S93 CONN EDGECARD 80POS DIP .100 SLD
MIC5333-PPYMT TR IC REG LDO 3V .3A 10TMLF
ISL9003AIEJZ-T IC REG LDO 2.8V .15A SC70-5
AS1363-BSTT-15 IC REG LDO 1.5V .5A SOT23-6
鐩搁棞(gu膩n)浠g悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
LFXP20E-3F388C 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 268 IO 1. 2V -3 Spd RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
LFXP20E-3F388I 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 268 IO 1. 2V -3 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
LFXP20E-3F484C 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 340 IO 1. 2V -3 Spd RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
LFXP20E-3F484I 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 340 IO 1. 2V -3 Spd I RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256
LFXP20E-3FN256C 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫村彲绶ㄧ▼闁€闄e垪 19.7K LUTs 188 IO 1. 2V -3 Spd RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256