Min. Delay of Clock to ddr_dq_in flops = t
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寤犲晢锛� Lattice Semiconductor Corporation
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Board Timing Guidelines
Lattice Semiconductor
for the DDR SDRAM Controller IP Core
17-4
Min. Delay of Clock to ddr_dq_in flops = tFPGA_CLK (min) + tSKEW + tFDH
To meet hold time at ddr_dq_in flops, Data Delay - Clock Delay > 0
Therefore:
tDDR_CLK (min) + tBDC + tAC (min) + tBDD + tPD - tFPGA_CLK (min) - tSKEW - tFDH > 0
Isolating the board delays, we get:
(tBDD + tBDC) > tFPGA_CLK (min) + tSKEW + tFDH - tDDR_CLK (min) - tAC (min) - tPD
(tBDD + tBDC) > (1.239) ns + 0.3 + (-1.609ns) - (1.138) - (-0.75) - 0
(tBDD + tBDC) > -0.458 ns
Conclusion: To meet read set-up and hold timing, board delay for ddr_dq, ddr_clk and ddr_clk_n should be:
-0.458ns < (tBDD + tBDC) < -0.03ns
Write Operation
For a proper write operation, data (ddr_dq) should meet set-up (tDS) and hold (tDH) time requirements of DDR
SDRAM with respect to ddr_dqs signal. The ddr_dqs signal is generated with respect to negative edge of
pll_nclk
and data ddr_dq out is generated with respect to positive edge of pll_nclk as shown in Figure 17-3.
As a result, 1/2 clk2x (3.75ns/2) is provided as set-up and hold for ddr_dq_out with respect to dqs_out.
For maximum set-up and hold margin, the ddr_dqs and ddr_dq traces on the board should be matched.
Table 17-2. Write Operation Timing Arcs
Figure 17-3. Write Timing Diagram
Write Set-up
Clock Delay = tCDQS + 1/2 clk2x - tDS + tBDDS
Data Delay = tCDQ + tBDD
Symbol
Description
ORCA 4
tDS
Set-up time required by the DQ with respect to DQS for DDR SDRAM.
0.75ns
tDH
Hold time required by the DQ with respect to DQS for DDR SDRAM.
0.75 ns
tCDQ
Clock-to-out timing for ddr_dq with respect to pll_nclk.鈥�
tCDQS
Clock-to-out timing for ddr_dqs with respect to pll_nclk.鈥�
tBDDS
Board delay of ddr_dqs from FPGA to DDR SDRAM pins.
鈥�
pll_nclk (clk2x)
dqs_out
ddr_dq_out
t
CDQS
t
CDQ
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