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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | LFECP33E-3FN484I |
| 寤犲晢锛� | Lattice Semiconductor Corporation |
| 鏂囦欢闋�(y猫)鏁�(sh霉)锛� | 85/163闋�(y猫) |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC FPGA 32.8KLUTS 484FPBGA |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | LatticeECP3 Introduction |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 60 |
| 绯诲垪锛� | ECP |
| 閭忚集鍏冧欢/鍠厓鏁�(sh霉)锛� | 32800 |
| RAM 浣嶇附瑷�(j矛)锛� | 434176 |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 360 |
| 闆绘簮闆诲锛� | 1.14 V ~ 1.26 V |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 宸ヤ綔婧害锛� | -40°C ~ 100°C |
| 灏佽/澶栨锛� | 484-BBGA |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 484-FPBGA锛�23x23锛� |
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2-25
Architecture
LatticeECP/EC Family Data Sheet
Figure 2-29. Output Register Block
Figure 2-30. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
D
Q
D
Q
D-Type
ONEG0
From
Routing
CLK1
Programmed
Control
DO
Latch
LE*
*Latch is transparent when input is low.
OPOS0
OUTDDN
/LATCH
0
1
0
1
To sysIO
Buffer
ODDRXB
LSR
Q
DB
CLK
DA
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
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| GSC65DRTI | CONN EDGECARD 130PS DIP .100 SLD |
| 24LC01BT-I/OT | IC EEPROM 1KBIT 400KHZ SOT23-5 |
| ACE50DHFT | CONN EDGECARD 100POS 1MM SMD |
| LFECP33E-4FN484C | IC FPGA 32.8KLUTS 360I/O 484-BGA |
| GMC65DRTI | CONN EDGECARD 130PS DIP .100 SLD |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
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| LFECP33E-3FN672C | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪 32.8K LUTs Pb-Free RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFECP33E-3FN672I | 鍔熻兘鎻忚堪:FPGA - 鐝�(xi脿n)鍫�(ch菐ng)鍙法绋嬮杸闄ｅ垪 32.8K LUTs 496 I/O RoHS:鍚� 鍒堕€犲晢:Altera Corporation 绯诲垪:Cyclone V E 鏌垫サ鏁�(sh霉)閲�: 閭忚集濉婃暩(sh霉)閲�:943 鍏�(n猫i)宓屽紡濉奟AM - EBR:1956 kbit 杓稿叆/杓稿嚭绔暩(sh霉)閲�:128 鏈€澶у伐浣滈牷鐜�:800 MHz 宸ヤ綔闆绘簮闆诲:1.1 V 鏈€澶у伐浣滄韩搴�:+ 70 C 瀹夎棰�(f膿ng)鏍�:SMD/SMT 灏佽 / 绠遍珨:FBGA-256 |
| LFECP33E-3Q208C | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFECP33E-3Q208I | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
| LFECP33E-3QN208C | 鍒堕€犲晢:LATTICE 鍒堕€犲晢鍏ㄧū:Lattice Semiconductor 鍔熻兘鎻忚堪:LatticeECP/EC Family Data Sheet |
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