參數(shù)資料
型號: LFEC3E-5FN256C
廠商: Lattice Semiconductor Corporation
文件頁數(shù): 35/163頁
文件大小: 0K
描述: IC FPGA 3.1KLUTS 256FPBGA
標(biāo)準(zhǔn)包裝: 90
系列: EC
邏輯元件/單元數(shù): 3100
RAM 位總計: 56320
輸入/輸出數(shù): 160
電源電壓: 1.14 V ~ 1.26 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 256-BGA
供應(yīng)商設(shè)備封裝: 256-FPBGA(17x17)
2-10
Architecture
LatticeECP/EC Family Data Sheet
grammed during configuration or can be adjusted dynamically. In dynamic mode, the PLL may lose lock after
adjustment and not relock until the tLOCK parameter has been satisfied. Additionally, the phase and duty cycle block
allows the user to adjust the phase and duty cycle of the CLKOS output.
The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated
with it: input clock divider, feedback divider, post scalar divider and secondary clock divider. The input clock divider
is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. The post
scalar divider allows the VCO to operate at higher frequencies than the clock output, thereby increasing the fre-
quency range. The secondary divider is used to derive lower frequency outputs.
Figure 2-11. PLL Diagram
Figure 2-12 shows the available macros for the PLL. Table 2-5 provides signal description of the PLL Block.
Figure 2-12. PLL Primitive
VCO
CLKOS
CLKOK
LOCK
RST
CLKFB
from CLKOP
(PLL internal),
from clock net
(CLKOP) or
from a user
clock (PIN or logic)
Dynamic Delay Adjustment
Input Clock
Divider
(CLKI)
Feedback
Divider
(CLKFB)
Post Scalar
Divider
(CLKOP)
Phase/Duty
Select
Secondary
Clock
Divider
(CLKOK)
Delay
Adjust
Voltage
Controlled
Oscillator
CLKI
(from routing or
external pin)
CLKOP
EPLLB
CLKOP
CLKI
CLKFB
LOCK
EHXPLLB
CLKOS
CLKI
CLKFB
CLKOK
LOCK
RST
CLKOP
DDAIZR
DDAILAG
DDA MODE
DDAIDEL[2:0]
DDAOZR
DDAOLAG
DDAODEL[2:0]
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