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參數(shù)資料
| 型號(hào)： | LF6197 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 160 ns Monolithic Sample-and-Hold Amplifier |
| 中文描述： | 160納秒單片采樣保持放大器 |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大小： | 214K |
| 代理商： | LF6197 |
Test Circuit
TL/H/11381–4
FIGURE 1. Circuit configuration for the measurement of feedthrough attenuation. Input is connected
to ground in sample mode and is connected to 20 V
PP
, 100 kHz sine wave in hold mode.
Pin Descriptions
V
a
(12)
This is the positive power supply pin. A
a
5V to
a
15V supply voltage should be
applied to this pin and bypassed to
ground with a 0.1
m
F ceramic capacitor
in parallel with a 4.7
m
F tantalum capaci-
tor.
V
b
(4)
This is the negative power supply pin. A
b
5V to
b
15V supply voltage should be
applied to this pin and bypassed to
ground with a 0.1
m
F ceramic capacitor
in parallel with a 4.7
m
F tantalum capaci-
tor.
GND (9)
This is the ground reference pin. All sig-
nals are referenced to the potential at
this pin.
b
Input (1)
This is the inverting input of the ‘‘sam-
ple’’
amplifier.
Connecting
through a resistor to the output will con-
figure the sample-and-hold amplifier for
unity gain. Other inverting and non-in-
verting gains can be set by applying the
familiar op amp feedback topologies.
For stability reasons, stray capacitance
from the inverting input to ground should
be minimized.
this
pin
a
Input (2)
This is the non-inverting input of the
‘‘sample’’ amplifier. This pin should be
driven from a low impedance source.
Output (5)
This is the output of the sample-and-
hold amplifier.
LR1 (10)
This is the Logic Reference 1 input. By
applying the appropriate logic threshold
at this pin, the sample-and-hold amplifi-
er’s logic input can be made either CMOS
or ECL compatible. For TTL logic levels,
this pin should remain unconnected.
LR2 (13)
This is the Logic Reference 2 input. For
TTL logic levels, this pin should be con-
nected to ground; this sets the logic
threshold at the logic comparator’s invert-
ing pin at 1.4V. For CMOS or ECL logic
levels this pin should either remain un-
connected or connected to pin 10.
Logic Input (11)
This is the logic control input pin. A logic
low at this pin will configure the amplifier
in the ‘‘sample’’ mode while a logic high
will configure the amplifier in the ‘‘hold’’
mode. The TTL, CMOS, or ECL logic
compatibility will be determined by the
voltage threshold set at the logic compar-
ator’s inverting input.
Zener Reference For optimum acquisition and settling
Output (14)
times, this pin must be bypassed to
ground with a 0.01
m
F capacitor. Further-
more, for
g
5V supply operation, this pin
must be biased at 2.5V from a low imped-
ance source.
NC (3,6,7,8)
No connection.
7
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