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參數(shù)資料
| 型號(hào)： | LF6197 |
| 廠商： | National Semiconductor Corporation |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | 160 ns Monolithic Sample-and-Hold Amplifier |
| 中文描述： | 160納秒單片采樣保持放大器 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 214K |
| 代理商： | LF6197 |
Electrical Characteristics
(Continued)
Note 1:
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2:
Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 3:
The maximum power dissipation must be derated at elevated temperatures and is dictated by T
Jmax
,
H
JA
, and the ambient temperature T
A
. The maximum
allowable power dissipation is P
D
e
(T
Jmax
b
T
A
)/
H
JA
or the number given in the Absolute Maximum Ratings, whichever is lower. For this device, T
Jmax
e
150
§
C
and
i
JA
e
125
§
C/W. The Power Derating Curve shows the safe thermal operating area for this device.
Note 4:
Continuous short-circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature of 150
§
C.
Note 5:
Human body model, 100 pF capacitor discharged through a 1.5 k
X
resistor.
Note 6:
Typicals are at T
A
e
25
§
C and represent the most likely parametric norm.
Note 7:
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 8:
Operation at
g
5V requires that pin 14 be forced to 2.5V.
Note 9:
Gain error is calculated from the measured open loop gain.
Note 10:
The acquisition time of the LF6197 has been measured when the device has been configured as an inverting amplifier with a gain of
b
1, feedback
resistor of 2 k
X
, feedback capacitor of 1 pF, and a total load resistor of 1 k
X
.
Note 11:
Hold step is measured with the LF6197 configured as a unity gain follower and input connected to ground. A TTL pulse with 4 ns rise and fall times is
applied to the logic input; the hold step is dependent on the slew rate of the logic input pulse.
Note 12:
See test circuit, Figure 1.
Note 13:
Full power bandwidth is calculated using FPBW
e
SR/(2
q
V
P
); where SR is the measured slew rate and V
P
is the peak voltage.
4
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