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參數(shù)資料
| 型號： | LCK4950 |
| 英文描述： | Low-Voltage PLL Clock Driver |
| 中文描述： | 低電壓PLL時鐘驅(qū)動器 |
| 文件頁數(shù)： | 14/16頁 |
| 文件大?。?/td> | 215K |
| 代理商： | LCK4950 |
14
Agere Systems Inc.
Data Sheet
November 2001
Low-Voltage PLL Clock Driver
LCK4950
Electrical Characteristics
(continued)
Driving Transmission Lines
The LCK4950 clock driver was designed to drive high-speed signals in a terminated transmission line environment.
The output drivers were designed to exhibit the lowest impedance possible to provide the optimum flexibility to the
user. With an output impedance of less than 10
,
the drivers can drive either parallel-terminated or series-
terminated transmission lines.
Point-to-point distribution of signals is the method of choice in most high-performance clock networks. In a point-to-
point scheme, either series-terminated or parallel-terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50
resistance to V
DD
/2. Only a single terminated line
can be driven by each output of the LCK4950 clock driver because this technique draws a fairly high level of dc
current. For the series driven case, however, there is no dc current draw and the outputs can drive multiple series-
terminated lines. Figure 10 illustrates an output driving a single series-terminated line.
5-9709 (F)
Figure 10. Single Transmission Line
The situation in Figure 11 should be used to better match the impedances when driving multiple lines. In this case,
the series-terminating resistors are reduced so when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
5-9710 (F)
Figure 11. Optimized Dual Line Termination
IN
OUTPUT
BUFFER
7
R
S
= 43
Z
O
= 50
OutA
OUTPUT
BUFFER
7
R
S
= 36
Z
O
= 50
R
S
= 36
Z
O
= 50
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