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參數(shù)資料
| 型號： | LC877424A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | 8 Bit Single Chip Microcontroller Incorporating 48K/40K/32K/24K Byte ROM and 1536 byte RAM on Chip |
| 中文描述： | 8位單片機微控制器納入48K/40K/32K/24K字節(jié)ROM和1536字節(jié)的片上內(nèi)存 |
| 文件頁數(shù)： | 13/22頁 |
| 文件大小： | 342K |
| 代理商： | LC877424A |
LC877448A/40A/32A/24A
No.7776-13/22
Continued from preceding page.
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
Pin capacitance
CP
All pins
All other terminals
connected to VSS.
f=1MHz
Ta=25
°
C
2.5 to 6.0
10
pF
Input sensitivity
Vsen
Port 87 small signal
input
2.5 to 6.0
0.12VD
D
Vp-p
Serial Input / Output Characteristics
/ Ta=-30
°
C to +70
°
C, VSS1=VSS2=VSS3=0V
Parameter
Symbol
Pins
Conditions
VDD [V]
min
typ
max
unit
[Serial clock]
[Input clock]
Cycle time
tSCK1
4/3
tSCKL1
2/3
Low level pulse
width
tSCKLA1
2/3
tSCKH1
2/3
High level pulse
width
tSCKHA1
SCK0(P12)
Refer to figure 6
2.5 to 6.0
5
Cycle time
tSCK2
2
Low level pulse
width
tSCKL2
1
High level pulse
width
tSCKH2
SCK1(P15)
Refer to figure 6
2.5 to 6.0
1
tCYC
[Output clock]
Cycle time
tSCK3
4/3
tCYC
tSCKL3
1/2
Low level pulse
width
tSCKLA2
3/4
tSCKH3
1/2
High level pulse
width
tSCKHA2
SCK0(P12)
CMOS output
Refer to figure 6
2.5 to 6.0
2
tSCK
Cycle time
tSCK4
2
tCYC
Low level pulse
width
tSCKL4
1/2
High level pulse
width
tSCKH4
SCK1(P15)
CMOS output
Refer to figure 6
2.5 to 6.0
1/2
tSCK
[Serial input]
4.5 to 6.0
0.03
Data set-up time
tsDI
2.5 to 6.0
0.1
4.5 to 6.0
0.03
Data hold time
thDI
SI0(P11), SI1(P14),
SB0(P11), SB1(P14)
Measured with respect
to SIOCLK leading
edge
Refer to figure 6
2.5 to 6.0
0.1
μ
s
[Serial output]
4.5 to 6.0
1/3tCY
C
+0.05
Output delay time
tdDO
SO0(P10), SO1(P13),
SB0(P11), SB1(P14)
When port is open
drain: Time delay
from SIOCLK trailing
edge to the SO data
change
Refer to figure 6
2.5 to 6.0
1/3tCY
C
+0.25
μ
s
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| LC877432A | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:8 Bit Single Chip Microcontroller Incorporating 48K/40K/32K/24K Byte ROM and 1536 byte RAM on Chip |
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