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參數(shù)資料
| 型號(hào)： | LC866524A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-OR Gates 14-TSSOP -40 to 85 |
| 中文描述： | 四2正輸入或門(mén) 14-TSSOP封裝；-40℃到85℃ |
| 文件頁(yè)數(shù)： | 11/21頁(yè) |
| 文件大?。?/td> | 641K |
| 代理商： | LC866524A |
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LC866548/40/32/28/24A
No.6700-11/21
2. Recommended Operating Range at Ta=-30
°
C to +70
°
C, VSS1=VSS2=0V
Ratings
typ.
Parameter
Symbol
Pins
Conditions
VDD[V]
min.
4.5
max.
6.0
unit
Operating
supply voltage
range
Hold voltage
VDD(1)
VDD1=VDD2
=VDD3=VDD4
0.98
μ
s
≤
tCYC
tCYC
≤
400
μ
s
VHD
VDD1=VDD2
RAMs and the
Registers hold voltage
at HOLD mode.
2.0
6.0
Pull-down
voltage
Input high
voltage
VP
VP
4.5 - 6.0
-35
VDD
VIH(1)
Port 0 at CMOS
output option
Port 0 at N-ch
open drain output
Port 1
Ports 72, 73
Port 3 at CMOS
output option
Port 3 at N-ch
open drain output
Port 70
port input
/interrupt
Port 71
RES
Port 70
Watchdog timer
Port 8
Ports
74
, 75
S16 - S51
Output disable
4.5 - 6.0
0.33VDD
+1.0
VDD
13.5
VIH(2)
Output disable
4.5 - 6.0
0.75VDD
VIH(3)
Output disable
4.5 - 6.0
0.75VDD
VDD
VIH(4)
Output disable Tr.
OFF
Output disable
4.5 - 6.0
0.75VDD
13.5
VDD
VIH(5)
4.5 - 6.0
0.75VDD
VIH(6)
Output disable
4.5 - 6.0 0.9VDD
VDD
VDD
VDD
0.2VDD
VIH(7)
Output disable
4.5 - 6.0
0.75VDD
VIH(8)
Output P-channel Tr.
OFF
Output disable
4.5 - 6.0
0.33VDD
+1.0
VSS
VIL(1)
Port 0 at CMOS
output option
Port 0 at N-ch
open drain output
Ports 1, 3
Ports 72, 73
Port 70
port input
/interrupt
Port 71
RES
Port 70
Watchdog timer
Port 8
Ports
74
, 75
S16 - S51
4.5 - 6.0
VIL(2)
Output disable
4.5 - 6.0
VSS
0.25VDD
VIL(3)
Output disable
4.5 - 6.0
VSS
0.25VDD
VIL(4)
Output disable
4.5 - 6.0
VSS
0.25VDD
VIL(5)
Output disable
4.5 - 6.0
VSS
0.8VDD
-1.0
0.25VDD
VIL(6)
Output disable
4.5 - 6.0
VSS
Input low
voltage
VIL(7)
Output P-channel Tr.
OFF
4.5 - 6.0
VP
0.2VDD
V
Operation
cycle time
tCYC
4.5 - 6.0
0.98
400
μ
s
(continue)
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