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參數(shù)資料
| 型號： | LC83200W |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 466K |
| 代理商： | LC83200W |
LC83200W
No.7902-4/11
Pin Assignment
Pin Functions
Audio data input (serial)
: L, R, Ls, Rs, C, and LFE
Audio data output (serial)
: L and R
Microcontroller interface
: For serial control register configuration
Parallel control port
: For Parallel control register configuration
RESET & PLL stop
: Reset & PLL STOP pin
PLL related
: Generates internal clock from external clock input with PLL.
Power supply
: Logic system: 2.5V
I/O system: 3.3V
Independent PLL power supply
Test pins
: For test purposes
TEST(SCAN_EN)
V
DD
6(Logic)
VDD1(I/O)
SCLOCK(BITCLOCK)
SDO
TEST(BIST_MODE)
SDI0(L/R)
AVSS
SDI1(LS/RS)
TEST(SCAN_MODE)
SDI2(C/LFE)
VSS1
LC83200W TOP
SQFP48
LRCLOCK
TEST
(NC)
RESET
10k
10k
10k
10k
10k
10k
10k
10k
5.6k
100
10k
*k
CON
10k
10k
10k
10k
10k
10k
10k
10k
Top view
0.1
F
0.1
F
*
F
0.
1
F
33
F(OS-Con)
CON
CON
STEREO
MUTE
EXT
V
SS
6
V
DD
5(Logic)
CMODE
ENABLE
CLOCK
DATA
TEST(BIST_DONE)
PLL
STOP
AV
DD
R
PDO
PLL_CLOCK_SW
VCNT
PLL_TEST_CLOCK
MP3
LC89056
V
DD
3(I/O)
V
SS
3
PLL1
PLL0
MCLOCK
VSS5
VSS4
TEST(BIST_FAIL)
FMT2
FMT1
FMT0
PRG4
PRG3
PRG2
VDD4
(Logic)
PRG1
PRG0
1
9
2
3
4
5
7
8
6
10
11
12
13
14
15
16
23
24
17
20
18
21
22
19
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
44
45
46
47
48
43
DIR
+
DAC
DSP
VDD3.3V
VDD2.5V
AVDD2.5V
GND
ILC05575
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