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參數(shù)資料
| 型號(hào)： | LC83200W |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁(yè)數(shù)： | 11/11頁(yè) |
| 文件大小： | 466K |
| 代理商： | LC83200W |
LC83200W
No.7902-9/11
Other Details
MUTE: This applies the muting function to the IC chip.
STEREO: This outputs the SDI0 input audio data to SDO using the bypass. The SDI1 data and SDI2 data are ignored.
When Bypass on is set for STEREO, the MUTE setting is canceled.
PLL STOP: This shuts down the PLL clock, and establishes power-saving mode to reduce power consumption. After
this setting has been released, resetting must be initiated for the IC, and the control registers must be set
again.
Stereo Mixdown: The calculation formulas below are employed for the stereo down-mix filter which is used in this
mode.
Lo = 0.5 (L+0.707C+LS+LFE)
Ro = 0.5 (R+0.707C+RS+LFE)
Table of DH processing correspondences by sampling frequency: The LC83200W has ROM coefficients that are used
for the processing of the places marked with “ ” in the table below.
Table 5
32kHz sample
44.1kHz sample
48kHz sample
96kHz sample
2ch
5.1ch
2ch
5.1ch
2ch
5.1ch
2ch
5.1ch
DH1
×
DH2
×
DH3
×
Mixdown
L/R Bypass
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