參數(shù)資料
型號: LC7872E
廠商: Sanyo Electric Co.,Ltd.
英文描述: CD Graphics Decoder
中文描述: 光盤圖形解碼器
文件頁數(shù): 9/17頁
文件大?。?/td> 299K
代理商: LC7872E
Pin Functions
No. 4868-9/17
LC7872E
Pin No.
Symbol
I/O
Function
1
S1
I
S1
S2
CD DSP
CD DSP selection
0
0
LC7861N/67
2
S2
I
1
0
LC7860K/63
1
1
LC7868/69/681
3
SBCK
O
Subcode R to W readout clock
4
SFSY
I
Subcode frame synchronization signal
5
PW
I
Subcode R to W data
6
SBSY
I
Subcode block synchronization signal
7
V
DD
1
CE
Digital system power supply
8
I
Serial input or control pin during serial output
9
DO
O
Serial data output (N-ch open drain)
10
DI
I
Serial data input
11
CL
I
Serial data I/O clock
12
MUTE
I
Control signal that invalidates the subcode data
13
V
SS
1
WE
Digital system ground
14
O
DRAM control
15
RAS
O
DRAM control
16
A0
O
DRAM address
17
A1
O
DRAM address
18
A2
O
DRAM address
19
A3
O
DRAM address
20
A4
O
DRAM address
21
A5
O
DRAM address
22
A6
O
DRAM address
23
A7
O
DRAM address
24
DB0
I/O
DRAM data
25
CAS
O
DRAM control
26
DB1
I/O
DRAM data
27
OE
O
DRAM control
28
DB2
I/O
DRAM data
29
DB3
I/O
DRAM data
30
CB
I
High: color bar output
Low: normal mode
(pull-down resistor built in)
31
CDGM
O
Outputs a high level when a CD-G disk detected
32
TRANS0
O
Transparency digital output
33
TRANS1
O
Transparency digital output
34
TRANS2
O
Transparency digital output
35
TRANS3
O
Transparency digital output
36
TRANS4
O
Transparency digital output
37
TRANS5
O
Transparency digital output
38
V
SS
2
V
DD
2
BIAS
Composite video D/A converter ground
39
Composite video D/A converter power supply
40
O
Ripple exclusion capacitor connection
41
VIDEO
O
Composite video output (8-bit D/A converter output)
42
TEST
I
Test pin. Must be tied low in normal operation (pull-down resistor built in)
43
LINE
I
When pin NP2 is high: High: 263H, Low: 262H
When pin NP2 is low: High: 312H, Low: 314H
44
FSCIN
I
Subcarrier clock input (feedback resistor built in)
45
VSYNC
O
Vertical synchronization signal output
46
TEST1
I
Test pin. Must be tied low in normal operation (pull-down resistor built in)
47
YS
O
Superimposition control output
48
CSYNC
O
Composite synchronization signal output
49
4FSC2
I
Superimposition mode external clock input (feedback resistor built in)
50
EFLG
O
Error state monitor
Continued on next page.
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參數(shù)描述
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