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參數(shù)資料
| 型號(hào)： | LC78631E |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 16-bit fixed point DSP with Flash |
| 中文描述： | 具有閃存的 16 位定點(diǎn) DSP |
| 文件頁數(shù)： | 10/34頁 |
| 文件大小： | 503K |
| 代理商： | LC78631E |
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No. 5342-10/34
LC78631E
CD D/A Converter Block Diagram
1. HF signal input circuit; Pin 11: EFMI, pin 9: EFMO, pin 79: DEFI, pin 13: CLV
+
When an HF signal is input to EFMI, the circuit slices it at an optimal
level to produce an EFM (NRZ) signal.
To deal with defects, if the DEFI pin (pin 79) goes high, the slice
level control output (EFMO, pin 9) goes to the high-impedance state
and the slice level is held. However, this function only operates when
CLV is in phase control mode, i.e., when the V/P pin (pin 15) is low.
This function can be formed by combining with the DEF pin on the
LA9230/40 Series LSI.
Note: If the EFMI and CLV
+
lines are placed too close together,
spurious radiation (induced noise) can degrade the error rate.
Therefore we recommend laying a ground or V
DD
shielding
line between these lines.
2. PLL clock reproduction circuit; Pin 2: PDO2, pin 3: PDO1, pin 5: FR, pin 7: ISET, pin 21: PCK
This block includes a VCO circuit, and a PLL
circuit is formed using external resistors and
capacitors. ISET is the charge pump reference
current, PDO1 and PDO2 are the loop filters, and
FR determines the VCO frequency range.
(Reference values)
R1 = 68 k
, C1 = 0.1 μF
R2 = 680
, C2 = 0.1 μF
R3 = 680
, C3 = 0.047 μF
R4 = 1.2 k
3. Synchronization detection monitor; Pin 22: FSEQ
This pin outputs a high level when the frame sync (positive synchronizing signal), which is read by PCK from the
EFM signal, and the timing (the inserted synchronizing signal), which is generated by a counter, agree. Thus this pin
functions as a synchronization monitor. Note that it is held high during one frame.
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