參數(shù)資料
型號: LC78626KE
廠商: Sanyo Electric Co.,Ltd.
英文描述: Compact Disc Player DSP(用于CD播放器的8位DSP)
中文描述: 光碟機(jī)的DSP(用于光盤播放器的8位數(shù)字信號處理器)
文件頁數(shù): 9/34頁
文件大小: 387K
代理商: LC78626KE
No. 5995-9/34
LC78626KE
Continued from preceding page.
Pin
No.
Pin
Name
I/O
Description
Output pin states
during reset
34
CONT3/SBCK
I/O
Input mode
35
CONT4/SFSY
I/O
Input mode
36
CONT5/PW
I/O
Input mode
37
SBSY
O
Subcode block sync signal output
Undefined
38
TEST3
I
Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
39
DOUT
O
Digital output. EIAJ format.
Undefined
40
TEST4
I
Test input. Equipped with an internal pull-down resistor. Must be connected to 0 V.
41
16M/NGJ
O
Clock output
42
4.2M
O
4.2336 MHz output
Clock output
43
EFLG
O
C1, C2, one error, two error error correction monitor output
Undefined
44
FSX
O
7.35 kHz sync signal output (frequency divided from the crystal oscillator).
Undefined
45
EMPH
O
Deemphasis monitor output. When high level, a deemphasis disk is being played back.
Low-level output
46
C2F
O
C2 flag output
Undefined
47
TOUT
O
Test output. Under normal operation, this should be left open.
Undefined
48
MR1
I
DRAM switch: high : 1M, low : 4M
1 M: high, low 4 M: low, low 16 M: low, high 4 M X 2: high, high (MR1, MR2)
49
MR2
I
50
TESD
I
Test input. Must be connected to 0V.
51
MUTESL
O
L channel mute output
High-level output
52
LV
DD
LCHO
P
L channel power supply
53
AO
L channel output
54
L/RV
SS
RCHO
P
For the one-bit D/A
L/R channel ground. Must be connected to 0 V.
55
AO
converter
R channel output
56
RV
DD
MUTER
P
R channel power supply
57
O
R channel mute output
High-level output
58
XV
DD
XOUT
P
Crystal oscillator power supply
59
O
16.9344 MHz crystal oscillator connection
60
XIN
I
61
XV
SS
RWC
P
Crystal oscillator ground. Must be connected to 0 V.
62
I
Read/write control input. Schmidt input.
63
COIN
I
Microcontroller command input
64
CQCK
I
Input pin for the command input latch clock and the subcode readout clock. Schmitt input.
65
SQOUT
O
Subcode Q output
Undefined
66
WRQ
O
Subcode Q output standby output
Undefined
67
FMT
I
Operating mode switch: high: shock proof, low: through.
68
EMPP
O
DRAM empty (an RZP pulse is output when the DRAM is empty).
Low-level output
69
RES
I
External reset input: low reset (all internal blocks are reinitialized).
Continued on next page.
General I/O pin 3. This controls the commands from the microcontroller. This pin is shared exclusively with
the subcode read clock input (SBCK). When not used, either set this as an input port and connect to 0 V, or
set this as an output port and leave it open.
General I/O pin 4. This controls the commands from the microcontroller. This pin is shared exclusively with
the subcode frame sync signal output (SFSY). When not used, either set this as an input port and connect
to 0 V, or set this as an output port and leave it open.
General I/O pin 5. This controls the commands from the microcontroller. This pin is shared, exclusively, with
the subcode P, Q, R, S, T, U, V, W output (PW). When not used, either set this as an input port and connect
to 0 V, or set this as an output port and leave it open.
Shared function pin that functions either as the 16.9344 MHz output (16M) or as the C2 flag data continuity check
start signal (detection start is indicated by a low to high transition). Controlled by microcontroller commands.
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