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參數(shù)資料
| 型號： | LC7216M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | MINI, FP-20 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 299K |
| 代理商： | LC7216M |
2. When the general-purpose counter is used the DO pin can be used to check for completion of the general-purpose
counter measurement.
When CTEN is set to 1, DO going low due to changes in IN0 is disabled and DO is set high automatically.
DO is automatically set low when the general-purpose counter measurement completes.
(That is, DO can be used to check for measurement completion.)
PLL Unlock Data Read Out Procedure
The internal data UL(n) is set on the rising edge of ERROR
and reset on the rising edge of CE
.
The ERROR data UL(n) from before the previous CE
rising edge can be read out in mode 3 (data output).
In the example above, the data from the period between t0 and t1 is read out.
No. 3355-13/15
LC7216M
UL (n)
3210
ERROR < 0.55 s →
0000
0.55 s ≤ ERROR < 1.11 s →
1000
1.11 s ≤ ERROR < 2.22 s →
1001
2.22 s ≤ ERROR < 3.33 s →
1011
3.33 s ≤ ERROR
→
1111
UL0 : 1.11 s
UL1 : 2.22 s
UL2 : 3.33 s
UL3 : 0.55 s
Each bit is set to 1 according to ERROR as described above.
ERROR: the phase difference (for a 7.2 MHz crystal)
Mode 1 or 2
(data input)
CTEN = 1
Mode 3
(data output)
* Output of the
measurement result
Mode 1 or 2
(data input)
CTEN = 0
Mode 1 or 2
(data input)
CTEN = 1
Mode 1 or 2
(data input)
CTEN = 0
Internal counter gate (GT)
: Counter data
: Internal state
Pin outputs
*DO going low due to
changes in IN0 is disabled.
Measurement
complete
Measurement
period
Measurement
period
Measurement
complete
signal
Measurement complete
Mode 1 or 2
(data input)
Mode 1 or 2
(data input)
Mode 3
(data output)
Data output for UL(n) = 1
Each bit is set to 1 according to ERROR as described above.
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