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參數(shù)資料
| 型號： | LC7216M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | MINI, FP-20 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 299K |
| 代理商： | LC7216M |
Pin Functions
Note: * The high and low level input voltages for the CE, CL, DI, IN0 and IN1 pins are VIH = 2.2 to 6.5 V and VIL = 0 to 0.7 V, regardless of the power
supply voltage VDD.
No. 3355-5/15
LC7216M
Pin No.
Symbol
I/O
Type
Function
1
20
16
15
18
17
19
2
4
3
5
XIN
XOUT
FMIN
AMIN
PD
VDD
VSS
CE
CL
DI
DO
Input
Output
Input
Three-state
—
Input*
Output
(N-channel
open drain)
Xtal OSC
Local oscillator signal
input
Local oscillator signal
input
Charge pump outputs
Power supply
Ground
Chip enable
Clock
Input data
Output data
Connections for a 7.2 MHz crystal oscillator
FMIN is selected when DV in the serial input data is set to 1.
Input frequency range: 10 to 130 MHz (70 mVrms minimum)
The signal passes through an internal divide-by-two prescaler and is then supplied to
the swallow counter.
Although the divisor setting is in the range 256 to 65,536, the actual divisor will be twice
the set value due to the presence of the internal divide-by-two prescaler.
AMIN is selected when DV in the serial input data is set to 0.
When SP in the serial input data is set to 1:
— Input frequency range: 2 to 40 MHz (70 mVrms minimum).
— The signal is supplied directly to the swallow counter without passing through the
internal divide-by-two prescaler.
— The divisor setting is in the range 256 to 65,536 and the actual divisor will be the
value set.
When SP in the serial input data is set to 0:
— Input frequency range: 0.5 to 10 MHz (70 mVrms minimum).
— The signal is supplied directly to a 12-bit programmable divider.
— The divisor setting is in the range 4 to 4,096 and the actual divisor will be the
value set.
PLL charge pump outputs. High levels are output from PD when the local
oscillator frequency divided by n is higher than the reference frequency, and low levels
are output when that frequency is lower than the reference frequency.
This pin go to the floating state when the frequencies agree.
The LC7216M power supply pin. A voltage of between 4.5 and 6.5 V must be provided
when the PLL is operating. The supply voltage can be lowered to 3.5 V when only
operating the crystal oscillator circuit to acquire the controller clock and the clock time
base outputs.
The LC7216M ground pin
This pin must be set high when inputting serial data (via DI) or when outputting serial
data (via DO).
The clock input used for data signal synchronization during serial data input (via DI) or
output (via DO).
Input pin used when transferring serial data from the controller to the LC7216M.
A total of 36 bits of data must be supplied to set up the LC7216M initial state.
Output pin used when transferring serial data to the controller from the LC7216M.
A total of 28 bits from an internal shift register can be output in synchronization with the
CL signal.
Continued on next page.
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