參數(shù)資料
型號: LC72148V
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝: SSOP-24
文件頁數(shù): 4/21頁
文件大小: 170K
代理商: LC72148V
No. 6974-12/21
LC72148V
Continued from preceding page.
Number
Control block/data
Description
Related data
Selects the crystal oscillator.
XS = 1: 7.2 MHz
= 0: 4.5 MHz
* The 4.5 MHz setting is selected after the power-on reset.
(11)
Crystal oscillator circuit
XS
Controls the phase comparator’s dead band.
The width of the dead band settings: DZA < DZB <DZC < DZD
* DZA is selected after the power-on reset. (We recommend using either DZD or DZC.)
(12)
Phase comparator
control data
DZ0, DZ1
This data forcibly sets the charge pump output to the low level (Vss).
DLC = 1: Low level
= 0: Normal operation
* When the circuit deadlocks due to the oscillator stopping when the PLL VCO control voltage
(Vtune) goes to 0 V, this bit can be used to clear the deadlocked state.
(Deadlock clear circuit)
This setting is set to normal operation after the power-on reset.
(13)
Charge pump control
data
Setting this bit to 1 causes a clock time base signal (8 Hz, 40% duty) to be output from the O-7
pin. (The OUT7 data is invalid in this mode.)
* TBC = 0 is selected after the power-on reset.
OUT7
(14)
Clock time base
TBC
IC test data.
TEST0
TEST1 All these bits must be set to 0.
TEST2
All these bits are set to 0 after the power-on reset.
(15)
IC test data
TEST0 to TEST2
DZ1
DZ0
Dead band mode
0
DZA
0
1
DZB
1
0
DZC
1
DZD
: Although these bits are initialized by the power-on reset circuit after power is applied, for safety, immediately after power is applied, always initialize this
setting by sending the CCB data.
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