參數(shù)資料
型號: LC72148V
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24
封裝: SSOP-24
文件頁數(shù): 19/21頁
文件大?。?/td> 170K
代理商: LC72148V
Procedures for input and output of serial data
Data is input and output using CCB (Computer Control Bus), which is SANYO’s audio IC serial bus format. This IC
adopts the 8-bit address version of the CCB format.
No. 6974-7/21
LC72148V
I/O mode
Address
Description
B0
B1
B2
B3
A0
A1
A2
A3
Control data input (serial data input) mode
1
IN1 (84)
0
1
0
1
0
32 bits of data are input.
See the “Structure of the DI control data (serial data input)” item for the content of the input data.
Control data input (serial data input) mode
2
IN2 (94)
1
0
1
0
1
0
32 bits of data are input.
See the “Structure of the DI control data (serial data input)” item for the content of the input data.
Data output (serial data output) mode
3
OUT (A4)
0
1
0
1
0
1
0
The number of bits of data output is equal to the number of clock cycles.
See the "Structure of the DO output data (serial data output)" item for the content of the
output data.
I/O mode determined
CE
CL
DI
B0
B1
B2
B3
A0
A1
A2
A3
First Data IN1/2
First Data OUT
DO
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