參數(shù)資料
型號: LC72147V
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
封裝: SSOP-24
文件頁數(shù): 8/22頁
文件大?。?/td> 154K
代理商: LC72147V
Programmable divider structure
General-purpose counter structure
The LC72147V’s general-purpose counter is a 20-bit binary counter.
The result of the count operation can be read out MSB first from the DO pin.
The measurement time when the general-purpose counter is used for frequency measurement is set to either 4, 8, 32, or
64 ms by the GT0 and GT1 bits. The frequency of the input to the HCTR pin can be measured by determining how many
pulses were input to the general-purpose counter during this measurement time.
No. 6675-16/22
LC72147V
4 bits
12 bits
Programmable
divider
Swallow
counter
E
fvco/N
PD
ferf
fvco = ferf
× N
FMIN
DVS
0 to 3
4 to 7
8 to 11 12 to 15 16 to 19
( FIF )
GT
GT1, GT0
M
S
B
L
S
B
CT
DO pin
General-purpose counter
(20-bit binary counter)
C = FIF
× GT
CTS
HCTR
1
2
4/8/32/64
msec
DVS
Set divisor (N)
Input frequency range (f(MHz))
FMIN
Minimum input sensitivity
1
272 to 65535
10
≤ f < 130
130
≤ f ≤ 180
Selected
40 mVrms
70 mVrms
0
Pulled down
Check signal frequency
X’tal OSC
4.5 MHz
7.2 MHz
10.25 MHz
10.35 MHz
fref = 30, 9, 3 kHz
fref : other than 30, 9, 3 kHz
Check signal
900 kHz
1025 kHz
1030 kHz
1150 kHz
The CTC data switches the input sensitivity. The input sensitivity is reduced when CTC is set to 1.
CTC
HCTR: Minimum input sensitivity rating
0.4
≤ f < 8
8
≤ f < 12
12
≤ f < 25
0 (Normal mode)
70 mVrms
(10 to 20 mVrms)
1 (Reduced sensitivity mode)
100 mVrms
(30 to 40 mVrms)
—: No sensitivity rating (not guaranteed)
( ): Rated value (reference value)
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