參數(shù)資料
型號(hào)： LC72147V
元件分類： PLL合成/DDS/VCOs
英文描述： PLL FREQUENCY SYNTHESIZER, 180 MHz, PDSO24
封裝： SSOP-24
文件頁(yè)數(shù)： 16/22頁(yè)
文件大?。?/td> 154K
代理商： LC72147V
No. 6675-3/22
LC72147V
Parameter
Symbol
Pin
Conditions
Ratings
Unit
Supply voltage
VDD max
VDD
–0.3 to +7.0
V
VIN1 max
CE, CL, DI, AIN
–0.3 to +7.0
Maximum input voltage
VIN2 max
XIN, FMIN, HCTR, I/O-4, I/O-5, ADC0, ADC1
–0.3 to Vreg + 0.3
V
VIN3 max
I/O-1 to I/O-3
–0.3 to +15
VO1 max
DO
–0.3 to +7.0
Maximum output voltage
VO2 max
XOUT, IFBC, I/O-4, I/O-5, PD, XBUF
–0.3 to Vreg + 0.3
V
VO3 max
I/O-1 to I/O-3, AOUT
–0.3 to +15
IO1 max
IFBC
0 to 1.0
IO2 max
I/O-4, I/O-5, XBUF
0 to 3.0
Maximum output current
IO3 max
DO
0 to 6.0
mA
IO4 max
I/O-1 to I/O-3
0 to 10
IO5 max
AOUT
0 to 35
Allowable power dissipation
Pd max
Ta
≤ 85°C
150
mW
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Specifications
Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V
Note: Power supply VDD - VSS, Vreg - VSS: Capacitors of at least 2000 pF must be inserted between these pins when this device is used.
Parameter
Symbol
Pin
Conditions
Ratings
Unit
min
typ
max
Supply voltage
VDD1VDD
4.5
6.5
V
VDD2VDD
Serial data retention voltage
2.5
Regulator output voltage
Vreg
4.5
≤ VDD ≤ 6.5 V
2.7
3.0
3.3
V
VIH1
CE, CL, DI,
2.2
6.5
V
High-level input voltage
I/O-1 to I/O-3
VIH2
I/O-4, I/O-5
2.2
Vreg
Low-level input voltage
VIL
CE, CL, DI,
0
0.8
V
I/O-1 to I/O-5
Output voltage
VO1
DO
0
6.5
V
VO2
I/O-1 to I/O-3
0
13
fIN1
XIN
Sine wave, capacitance coupled
1.0
8.0
Input frequency
fIN2
FMIN
Sine wave, capacitance coupled
10
180
MHz
fIN3
HCTR
Sine wave, capacitance coupled
0.4
25
Guaranteed crystal oscillator
X’tal1
XIN, XOUT
*1
4.0
7.0
MHz
frequency ranges
X’tal2
XIN, XOUT
*1
7.1
10.5
VIN1
XIN
200
900
VIN2-1
FMIN
10
≤ f < 130 MHz *2
40
900
Input amplitude
VIN2-2
FMIN
130
≤ f ≤ 180 MHz *2
70
900
mVrms
VIN3-1
HCTR
0.4
≤ f ≤ 25 MHz *3
70
900
VIN3-2
HCTR
8
≤ f ≤ 12 MHz *4
100
900
Input voltage range
VIN4
ADC0, ADC1
0
Vreg
V
Data setup time
tSU
DI, CL
*5
0.45
s
Data hold time
tHD
DI, CL
*5
0.45
s
Clock low-level period
tCL
CL
*5
0.45
s
Clock high-level period
tCH
CL
*5
0.45
s
CE wait time
tEL
CE, CL
*5
0.45
s
CE setup time
tES
CE, CL
*5
0.45
s
CE hold time
tEH
CE, CL
*5
0.45
s
Data latch change time
tLC
*5
0.45
s
Data output time
tDC
DO, CL
Depends on the value of the pull-up
0.2
s
tDH
DO, CE
resistor used.
Allowable Operating Ranges at Ta = –40 to 85°C, VSS = 0 V
Notes:1. Recommended crystal oscillator CI values
CI
≤ 120 (Crystal: 4.5 MHz), CI ≤ 70 (Crystal: 7.2, 10.25, or 10.35 MHz)
Note that the crystal oscillator circuit characteristics depend on the printed circuit board and the particular components used. We recommend
consulting the manufacturer of the crystal when designing this circuit.
2. Refer to the description of the structure of the programmable divider.
3. Serial data: CTC = 0
4. Serial data: CTC = 1
5. See the timing chart for serial data transfers.
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