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參數(shù)資料
| 型號(hào)： | LC72136NM |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 2/23頁 |
| 文件大小： | 318K |
| 代理商： | LC72136NM |
No. 5608-10/23
LC72136N, 72136NM
DI Control Data Functions
No.
Control block/data
Description
Related data
Programmable divider data Data that sets the programmable divider
P0 to P15
A binary value in which P15 is the MSB. The LSB changes depending on DVS and SNS.
Note: P0 to P3 are ignored when P4 is the LSB.
DVS, SNS
Selects the signal input pin (AMIN or FMIN) for the programmable divider, switches the
frequency range, and determines the BOF pin output state. (*: Don’t care.)
Note: See the “Programmable Divider” item for details.
Reference divider data
Reference frequency (fref) selection data
R0 to R3
Note: PLL INHIBIT
The programmable divider and IF counter blocks are stopped, the FMIN, AMIN,
and IFIN pins go to the pulled-down state, and the charge pump output pin goes to
the high-impedance state.
XS
Oscillator margin selection data
XS = 0: “Reduction mode” The oscillator margin is reduced and the crystal radiation
is reduced.
XS = 1: Normal mode.
Normal mode is selected following a power-on reset.
IF counter control data
IF counter measurement start specification
CTE
CTE = 1: Counter start
CTE = 0: Counter reset
GT0, GT1
IF counter measurement time determination
Note: See the “IF Counter Structure” item for details.
I/O port specification data
Data that specifies input or output for the I/O dual-use pins
IOC1, IOC2
Data: 0 = input mode, 1 = output mode
Output port data
BO1 to BO5, IO1, and IO2 output state data
BO1 to BO5, IO1, IO2
Data: 0 = open, 1 = low
“Data = 0: Open” is selected following a power-on reset.
(1)
(2)
(3)
(4)
(5)
IFS
IOC1
IOC2
DVS
SNS
LSB
Divisor setting (N)
Actual divisor
1
*
P0
272 to 65535
Twice the value of the setting
0
1
P0
272 to 65535
The value of the setting
0
P4
4 to 4095
The value of the setting
DVS
SNS
Input pin
Input frequency range
BOF pin
1
*
FMIN
10 to 160 MHz
Low
0
1
AMIN
2 to 40 MHz
Open
0
AMIN
0.5 to 10 MHz
Open
GT1
GT0
Measurement time (ms)
Wait time (ms)
0
4
3 to 4
0
1
8
3 to 4
1
0
32
7 to 8
1
64
7 to 8
R3
R2
R1
R0
Reference frequency (kHz)
0
25
0
1
25
0
1
0
25
0
1
25
0
1
0
12.5
0
1
0
1
6.25
0
1
0
3.125
0
1
3.125
1
0
5
1
0
1
5
1
0
1
0
5
1
0
1
0
3
1
0
1
15
1
0
PLL INHIBIT + Xtal OSC STOP
1
PLL INHIBIT
Continued on next page.
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相關(guān)代理商/技術(shù)參數(shù) |
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| LC72137 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
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| LC72140 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizers |
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