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參數(shù)資料
| 型號： | LC72134M |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO24 |
| 封裝： | MFP-24 |
| 文件頁數(shù)： | 15/27頁 |
| 文件大?。?/td> | 463K |
| 代理商： | LC72134M |
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Directly outputting the unlocked state to the DO pin
Since the unlocked state (high level when locked, low when unlocked) is output from the DO pin, the dummy data
processing described above is not necessary. After N is changed, applications can check the locked state after waiting
at least two periods of the reference frequency.
Clock Time Base Usage Notes
When using the clock time base output function, the output pin (BO1) pull-up resistor must have a value of over 100 k
.
The use of a Schmitt input in the microcontroller that accepts this signal is recommended to reduce chattering. This is to
prevent degradation of the VCO C/N characteristics when combining with a loop filter that uses the internal transistor
provided to form a low-pass filter. Since the ground for the clock time base output pin and the ground for the transistor
are common internally on the chip, applications must take care to minimize current fluctuations in the time base pin to
prevent degradation of the low-pass filter characteristics.
No. 5814-22/27
LC72134M
Wait at least 2 reference frequency periods
Valid output data is acquired by using an interval of at
least one reference frequency period
*: Even more reliable recognition of the locked state
can be achieved by performing several checks of the
state and requiring that the locked state be detected
sequentially
Divisor N changed (data input)
Dummy data output
Valid data output
Locked state check*
YES
NO
Outputting the unlocked state data in the serial data
In the LC72134M, the unlocked state data (UL), once set to the unlocked state, is not reset unless data is output (or
input). At the point of data output (1) in figure 3, the VCO frequency will be stable (locked), but since the divisor N
was changed and a data output operation has not yet been performed, the unlocked state data will indicate the unlocked
state. Thus even though the loop is stable (locked), the data will indicate that it is not. In cases such as this, the
application should treat the first data output after the value of N has been changed as dummy data, and consider the
second data output (at point (2) in the figure) as valid data.
<Flowchart for Lock Detection>
A09968
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| LC72135M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
| LC72135MA-AE | 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72135MA-Q-AE | 制造商:ON Semiconductor 功能描述:PLL FREQUENCY SYNTHESIZER - Tape and Reel 制造商:ON Semiconductor 功能描述:REEL / PLL FREQUENCY SYNTHESIZER |
| LC72135M-Q-TLM-E | 制造商:SANYO Semiconductor Co Ltd 功能描述: |
| LC72136 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer for Electronic Tuning |
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