參數(shù)資料
型號: LC72131KM
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: PLL合成/DDS/VCOs
英文描述: PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20
封裝: 0.300 INCH, MFP-20
文件頁數(shù): 4/22頁
文件大?。?/td> 200K
代理商: LC72131KM
LC72131K, 72131KM
No.A0788-12/22
Control Data Functions
No.
Control block/data
Functions
Related data
(1)
I/O port data
I2, I1
Latched from the pin states of the IO1 and IO2 I/O ports.
These values follow the pin states regardless of the input or output setting.
I1
← IO1 pin state
High: 1
I2
← IO2 pin state
Low: 0
IOC1
IOC2
(2)
PLL unlock data
UL
Latched from the state of the unlock detection circuit.
UL
← 0: Unlocked
UL
← 1: Locked or detection stopped mode
UL0
UL1
(3)
IF counter binary
counter
C19 to C0
Latched from the value of the IF counter (20-bit binary counter).
C19
← MSB of the binary counter
C0
← LSB of the binary counter
CTE
GT0
GT1
Serial Data I/O Methods
The LC72131 inputs and outputs data using the SANYO CCB (computer control bus) audio LSI serial bus format. This
LSI adopts an 8-bit address format CCB.
Address
I/O mode
B0
B1
B2
B3
A0
A1
A2
A3
Function
[1]
IN1 (82)
0
1
0
1
0
Control data input mode (serial data input)
24 data bits are input.
See the “DI Control Data (serial data input) Structure” item for details
on the meaning of the input data.
[2]
IN2 (92)
1
0
1
0
1
0
Control data input mode (serial data input)
24 data bits are input.
See the “DI Control Data (serial data input) Structure” item for details
on the meaning of the input data.
[3]
OUT (A2)
0
1
0
1
0
1
0
Data output mode (serial data output)
The number of bits output is equal to the number of clock cycles.
See the “DO Control Data (serial data output) Structure” item for details
on the meaning of the output data.
(2)
(1)
First Data IN1/2
First Data OUT
A3
A2
A1
A0
B3
B2
B1
B0
DI
I/O mode determined
CE
CL
(2)
(1) CL: Normal high
(2) CL: Normal low
(1)
DO
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