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參數(shù)資料
| 型號(hào)： | LC72131KM |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | PLL合成/DDS/VCOs |
| 英文描述： | PLL FREQUENCY SYNTHESIZER, 40 MHz, PDSO20 |
| 封裝： | 0.300 INCH, MFP-20 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 200K |
| 代理商： | LC72131KM |
LC72131K, 72131KM
No.A0788-10/22
Continued from preceding page.
No.
Control block/data
Functions
Related data
(4)
I/O port specification
data
IOC1, IOC2
Specifies the I/O direction for the bidirectional pins IO1 and IO2.
Data: 0=input mode, 1=output mode
(5)
Output port data
BO1 to BO4
IO1, IO2
Data that determines the output from the BO1 to BO4, IO1 and IO2 output ports
Data: 0=open, 1=low
The data=0 (open) state is selected after the power-on reset.
IOC1
IOC2
(6)
DO pin control data
DOC0
DOC1
DOC2
Data that determines the DO pin output
The open state is selected after the power-on reset.
Note: 1. end-UC: Check for IF counter measurement completion
(1) When end-UC is set and the IF counter is started (i.e., when CTE is changed from
zero to one), the DO pin automatically goes to the open state.
(2) When the IF counter measurement completes, the DO pin goes low to indicate the
measurement completion state.
(3) Depending on serial data I/O (CE: high) the DO pin goes to the open state.
Note: 2. Goes to the open state if the I/O pin is specified to be an output port.
Caution: The state of the DO pin during a data input period (an IN1 or IN2 mode period with CE
high) will be open, regardless of the state of the DO control data (DOC0 to DOC2).
Also, the DO pin during a data output period (an OUT mode period with CE high) will
output the contents of the internal DO serial data in synchronization with the CL pin
signal, regardless of the state of the DO control data (DOC0 to DOC2).
UL0, UL1
CTE
IOC1
IOC2
(7)
Unlock detection
data
UL0, UL1
Selects the phase error (
φE) detection width for checking PLL lock.
A phase error in excess of the specified detection width is seen as an unlocked state.
Note: In the unlocked state the DO pin goes low and the UL bit in the serial data becomes zero.
DOC0
DOC1
DOC2
Continued on next page.
Open
The IO1 pin state *2
The IO2 pin state *2
Open
Low when the unlock state is detected
end-UC *1
Open
Do pin state
DOC0
DOC1
0
1
0
1
0
1
0
1
0
1
0
1
0
DOC2
≈
(1) Count start
(3)CE: High
(2) Count end
DO pin
≈
Open
φE is output directry
φE is extended by 1 to 2ms
↑
stopped
0
±0.55μs
±1.11
Detector output
φE detection width
UL0
0
1
0
1
0
1
UL1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LC72131KMA | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:PLL Frequency Synthesizer |
| LC72131KMA-AE | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| LC72131M | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
| LC72131MDTRM | 制造商:Panasonic Industrial Company 功能描述:IC |
| LC72132 | 制造商:SANYO 制造商全稱:Sanyo Semicon Device 功能描述:AM/FM PLL Frequency Synthesizer |
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