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參數(shù)資料
| 型號： | LC66354C |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Quadruple 2-Input Positive-AND Gates 14-TSSOP -40 to 85 |
| 中文描述： | 四位單片機(jī)與4,6微控制器和8 KB的片上ROM |
| 文件頁數(shù)： | 10/21頁 |
| 文件大小： | 140K |
| 代理商： | LC66354C |
Electrical Characteristics
at Ta = –30 to +70°C, V
SS
= 0 V, V
DD
= 2.5 to 5.5 V unless otherwise specified.
No. 5484-10/21
LC66354C, 66356C, 66358C
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
P2, P3 (except for the P33/HOLD pin),
P4, P5, and P6: V
IN
= 13.5 V, with the output
Nch transistor off
I
IH
1
5.0
μA
1
Input high-level current
I
IH
2
P0, P1, PC, OSC1, RES, P33/HOLD:
V
IN
= V
DD
, with the output Nch transistor off
PD, PE, PC2, PC3: V
IN
= V
DD
,
with the output Nch transistor off
1.0
μA
1
I
IH
3
1.0
μA
1
I
IL
1
Input ports other than PD, PE, PC2, and PC3:
V
IN
= V
SS
, with the output Nch transistor off
PC2, PC3, PD, PE: V
IN
= V
SS
,
with the output Nch transistor off
–1.0
μA
2
Input low-level current
I
IL
2
–1.0
μA
2
P2, P3 (except for the P33/HOLD pin),
P6, and PC: I
OH
= –1 mA
P2, P3 (except for the P33/HOLD pin),
P6, and PC: I
OH
= –0.1 mA
P0, P1, P4, P5: I
OH
= –50 μA
P0, P1, P4, P5: I
OH
= –30 μA
P0, P1, P4, P5: V
IN
= V
SS
, V
DD
= 5.5 V
P0, P1, P2, P3, P4, P5, P6, and PC
(except for the P33/HOLD pin): I
OL
= 1.6 mA
P0, P1, P2, P3, P4, P5, P6, and PC
(except for the P33/HOLD pin): I
OL
= 8 mA
P2, P3, P4, P5, P6: V
IN
= 13.5 V
P0, P1, PC: V
IN
= V
DD
PD1 to PD3: V
IN
= V
SS
to V
DD
– 1.5 V,
V
DD
= 3.0 to 5.5 V
PD0: V
IN
= 1.5 to V
DD
, V
DD
= 3.0 to 5.5 V
V
DD
– 1.0
V
OH
1
V
3
V
DD
– 0.5
Output high-level voltage
V
OH
2
V
DD
– 1.0
V
DD
– 0.5
V
4
Output pull-up current
I
PO
–1.6
mA
4
V
OL
1
0.4
V
5
Output low-level voltage
V
OL
2
1.5
V
Output off leakage current
I
OFF
1
I
OFF
2
5.0
μA
5
1.0
μA
5
V
OFF
1
±50
±300
mV
Comparator offset voltage
V
OFF
2
±50
±300
mV
[Schmitt characteristics]
Hysteresis voltage
V
HIS
Vt H
0.1 V
DD
High-level threshold voltage
P2, P3, P5, P6, OSC1 (EXT), RES
0.5 V
DD
0.2 V
DD
0.8 V
DD
0.5 V
DD
V
Low-level threshold voltage
Vt L
V
[Ceramic oscillator]
Oscillator frequency
f
CF
f
CFS
OSC1, OSC2: Figure 2, 4 MHz
4.0
MHz
Oscillator stabilization time
Figure 3, 4 MHz
10
ms
[Serial clock]
Cycle time
Input
t
CKCY
0.9
μs
Output
2.0
Tcyc
Low-level and high-level Input
pulse widths
t
CKL
t
CKH
0.4
μs
Output
1.0
Tcyc
Rise an fall times
Output
t
CKR
, t
CKF
0.1
μs
[Serial input]
Data setup time
t
ICK
0.3
μs
Data hold time
t
CKI
0.3
μs
[Serial output]
SO0, SO1: With the timing of Figure 4 and
the test load of Figure 5. Stipulated with respect
to the falling edge (
↓
) of SCK0 or SCK1.
Output delay time
t
CKO
0.3
SI0, SI1: With the timing of Figure 4.
Stipulated with respect to the rising edge (
↑
) of
SCK0 or SCK1.
SCK0, SCK1: With the timing of Figure 4 and
the test load of Figure 5.
Continued on next page.
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