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參數(shù)資料
| 型號： | LC662508A |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Four-Bit Single-Chip Microcontrollers with 8, 12, and 16 KB of On-Chip ROM |
| 中文描述： | 四位單芯片8，12微控制器，和16 KB的片上ROM |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 151K |
| 代理商： | LC662508A |
No. 5997-14/17
LC662508A, 662512A, 662516A
Electrical Characteristics
at Ta = –30 to +70°C, V
SS
= 0 V, V
DD
= 3.0 to 5.5 V unless otherwise specified.
Parameter
Symbol
Conditions
min
typ
max
Unit
Note
P2, P3 (except for the P33/HOLD pin),
P61, and P63: V
IN
= 13.5 V, with the output
Nch transistor off
I
IH
1
5.0
μA
1
P0, P1, P4, P5, P6, P9, PC, TEST, RES, and
P33/HOLD (Does not apply to P61 and P63.):
V
IN
= V
DD
,
with the output Nch transistor off
Input high-level current
I
IH
2
1.0
μA
1
I
IH
3
PD, PE: V
IN
= V
DD
,
with the output Nch transistor off
1.0
μA
1
I
IL
1
Input ports other than PD and PE3:
V
IN
= V
SS
, with the output Nch transistor off
PD, PE: V
IN
= V
SS
,
with the output Nch transistor off
–1.0
μA
2
Input low-level current
I
IL
2
–1.0
μA
2
P2, P3 (except for the P33/HOLD pin),
P6, P8, P9, and PC: I
OH
= –1 mA
P2, P3 (except for the P33/HOLD pin),
P6, P8, P9, and PC: I
OH
= –0.1 mA
P0, P1, P4, P5, P7, PA, and PB
V
DD
– 1.0
Output high-level voltage
V
OH
1
V
3
V
DD
– 0.5
Value of the output pull-up resistor
R
PO
30
100
300
k
V
OL
1
P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB,
and PC
(except for the P33/HOLD pin): I
OL
= 1.6 mA
P0, P1, P2, P3, P4, P5, P6, P7, P8, P9, PA, PB,
and PC
(except for the P33/HOLD pin): I
OL
= 8 mA
P2, P3, P61, P63, and PA: V
IN
= 13.5 V
V
IN
= V
DD
P8: V
IN
= V
SS
0.4
V
5
Output low-level voltage
V
OL
2
1.5
V
5
I
OFF
1
5.0
μA
6
I
OFF
2
1.0
μA
6
Output off leakage current
I
OFF
3
–1.0
μA
7
[Schmitt characteristics]
Hysteresis voltage
V
HYS
Vt
H
Vt
L
0.1 V
DD
V
High-level threshold voltage
P2, P3, P5, P6, P61, P9, RES, OSC1 (EXT)
0.5 V
DD
0.2 V
DD
0.8 V
DD
0.5 V
DD
V
Low-level threshold voltage
V
[Ceramic oscillator]
Oscillator frequency
f
CF
f
CFS
OSC1, OSC2: See Figure 2. 4 MHz
4.0
MHz
Oscillator stabilization time
See Figure 3. 4 MHz
10.0
ms
[Serial clock]
Cycle time
Input
t
CKCY
0.9
μs
Output
2.0
Tcyc
Low-level and high-level Input
pulse widths
t
CKL
t
CKH
0.4
μs
Output
1.0
Tcyc
Rise an fall times
Output
t
CKR
, t
CKF
0.1
μs
[Serial input]
Data setup time
t
ICK
0.3
μs
Data hold time
t
CKI
0.3
μs
[Serial output]
SO0, SO1: With the timing of Figure 5 and the
test load of Figure 5. Stipulated with respect to
the falling edge (
↓
) of SCK0, SCK1.
Output delay time
t
CKO
0.3
μs
SI0, SI1: With the timing of Figure 4.
Stipulated with respect to the rising edge (
↑
) of
SCK0, SCK1.
SCK0, SCK1: With the timing of Figure 4 and
the test load of Figure 5.
Continued on next page.
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