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參數(shù)資料
| 型號： | LC65P1104 |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | On-Chip UVEPROM 4-Bit Single-Chip Microcontroller |
| 中文描述： | 片上UVEPROM 4位單片機 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 265K |
| 代理商： | LC65P1104 |
No. 5221-11/19
LC65E1104
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Serial output]
Output delay time
tCKO
SO: Specified from the falling edge of SCK.
Nch OD only, external 1k
, external 50 pF, Fig. 6
0.6
μs
[Pulse output]
Period
tPCY
64
×
tCYC
32
×
tCYC
± 10%
32
×
tCYC
± 10%
μs
High-level pulse width
tPH
μs
Low-level pulse width
tPL
μs
[AD conversion characteristics]
Resolution
V
DD
= 4.7 to 5.3 V
AV+ = V
DD
, AV– = V
SS
, V
DD
= 4.7 to 5.3 V
8
bits
Absolute accuracy
±1
±2
LSB
AD speed 1/1, at 26
×
tCYC, V
DD
= 4.7 to 5.3 V
72 (tCYC
= 2.77 μs)
312 (tCYC
= 12 μs)
Conversion time
TCAD
μs
AD speed 1/2, at 51
×
tCYC, V
DD
= 4.7 to 5.3 V
141 (tCYC
= 2.77 μs)
612 (tCYC
= 12 μs)
Reference input voltage
AV+
AV+: V
DD
= 4.7 to 5.3 V
AV–: V
DD
= 4.7 to 5.3 V
AV+, AV–: AV+ = V
DD
, V
DD
= 4.7 to 5.3 V, AV– = V
SS
AD0 to AD7: V
DD
= 4.7 to 5.3 V
AV–
V
DD
AV+
V
AV–
V
SS
75
Reference input current range
IRIF
150
300
μA
Analog input voltage range
VAIN
AV–
AV+
V
Port pins AD0 to AD7
Including output OFF leakage current. VAIN = V
DD
,
V
DD
= 4.7 to 5.3 V
1
Analog port input current
IAIN
μA
Port pins AD0 to AD7
VAIN = V
SS
, V
DD
= 4.7 to 5.3 V
–1
[Watchdog timer]
Cw
WDR: V
DD
= 3 to 6 V
WDR: V
DD
= 3 to 6 V
WDR: V
DD
= 3 to 6 V
WDR: Fig. 8, V
DD
= 3 to 6 V
WDR: Fig. 8, V
DD
= 3 to 6 V
WDR: V
DD
= 4 to 6 V
WDR: V
DD
= 4 to 6 V
WDR: V
DD
= 4 to 6 V
WDR: Fig. 8, V
DD
= 4 to 6 V
WDR: Fig. 8, V
DD
= 4 to 6 V
0.1 ± 5%
μF
k
μs
Guaranteed constant
*
7
Rw
680 ± 1%
RI
100 ± 1%
Clear time (discharge)
tWCT
100
Clear time (charge)
tWCCY
36
ms
Cw
0.047 ± 5%
μF
k
μs
Guaranteed constant
*
7
Rw
680 ± 1%
RI
100 ± 1%
Clear time (discharge)
tWCT
40
Clear time (charge)
tWCCY
18
ms
PE0: Fig. 7, tCYC = 4
×
system clock period,
Nch OD only, external 1 k
, external 50 pF
Note: 1. The LC65E1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 4 with circuit constants in the
guaranteed constants ranges is driven from within the IC.
2. Average over a 100 ms period
3. The operating supply voltage V
DD
must be held until standby mode is enterd after the execution of a HALT instruction. The PA3 pin must be free
from chattering during the HALT instruction cycle.
4. The OSC1 pin input circuit has Schmitt trigger characteristics when the 2-terminal RC oscillator option or the external clock oscillator option is
selected.
5. fCFOSC: oscillator frequency. The center frequency of a ceramic oscillator has a tolerance range of about 1% around the nominal value specified
by the manufacturer of the oscillator element. For details, refer to the specifications of the ceramic resonator.
6. TCYC = 4
×
system clock period
7. If the LC65E1104 is used in an environment subject to condensation, leakage between PE1 and adjacent pins and leakage associated with
external RCA circuits require special attention.
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